blob: bdb882ab88d4ab6aa45ac9e8ef8a749c7963aa2f [file] [log] [blame]
Achin Gupta7c88f3f2014-02-18 18:09:12 +00001/*
Douglas Raillard21362a92016-12-02 13:51:54 +00002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta7c88f3f2014-02-18 18:09:12 +00003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta7c88f3f2014-02-18 18:09:12 +000031#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +000032#include <asm_macros.S>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <tsp.h>
Achin Guptae1aa5162014-06-26 09:58:52 +010034#include <xlat_tables.h>
Dan Handleye2c27f52014-08-01 17:58:27 +010035#include "../tsp_private.h"
Achin Gupta7c88f3f2014-02-18 18:09:12 +000036
37
38 .globl tsp_entrypoint
Andrew Thoelke891c4ca2014-05-20 21:43:27 +010039 .globl tsp_vector_table
Achin Gupta7c88f3f2014-02-18 18:09:12 +000040
Soby Mathew9f71f702014-05-09 20:49:17 +010041
42
Achin Gupta7c88f3f2014-02-18 18:09:12 +000043 /* ---------------------------------------------
44 * Populate the params in x0-x7 from the pointer
45 * to the smc args structure in x0.
46 * ---------------------------------------------
47 */
48 .macro restore_args_call_smc
49 ldp x6, x7, [x0, #TSP_ARG6]
50 ldp x4, x5, [x0, #TSP_ARG4]
51 ldp x2, x3, [x0, #TSP_ARG2]
52 ldp x0, x1, [x0, #TSP_ARG0]
53 smc #0
54 .endm
55
Achin Gupta76717892014-05-09 11:42:56 +010056 .macro save_eret_context reg1 reg2
57 mrs \reg1, elr_el1
58 mrs \reg2, spsr_el1
59 stp \reg1, \reg2, [sp, #-0x10]!
60 stp x30, x18, [sp, #-0x10]!
61 .endm
62
63 .macro restore_eret_context reg1 reg2
64 ldp x30, x18, [sp], #0x10
65 ldp \reg1, \reg2, [sp], #0x10
66 msr elr_el1, \reg1
67 msr spsr_el1, \reg2
68 .endm
69
70 .section .text, "ax"
71 .align 3
Achin Gupta7c88f3f2014-02-18 18:09:12 +000072
Andrew Thoelke38bde412014-03-18 13:46:55 +000073func tsp_entrypoint
Achin Gupta7c88f3f2014-02-18 18:09:12 +000074
75 /* ---------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +000076 * Set the exception vector to something sane.
77 * ---------------------------------------------
78 */
Achin Guptaa4f50c22014-05-09 12:17:56 +010079 adr x0, tsp_exceptions
Achin Gupta7c88f3f2014-02-18 18:09:12 +000080 msr vbar_el1, x0
Achin Guptaed1744e2014-08-04 23:13:10 +010081 isb
Achin Gupta7c88f3f2014-02-18 18:09:12 +000082
83 /* ---------------------------------------------
Achin Guptaed1744e2014-08-04 23:13:10 +010084 * Enable the SError interrupt now that the
85 * exception vectors have been setup.
86 * ---------------------------------------------
87 */
88 msr daifclr, #DAIF_ABT_BIT
89
90 /* ---------------------------------------------
Achin Gupta9f098352014-07-18 18:38:28 +010091 * Enable the instruction cache, stack pointer
92 * and data access alignment checks
Achin Gupta7c88f3f2014-02-18 18:09:12 +000093 * ---------------------------------------------
94 */
Achin Gupta9f098352014-07-18 18:38:28 +010095 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
Achin Gupta7c88f3f2014-02-18 18:09:12 +000096 mrs x0, sctlr_el1
Achin Gupta9f098352014-07-18 18:38:28 +010097 orr x0, x0, x1
Achin Gupta7c88f3f2014-02-18 18:09:12 +000098 msr sctlr_el1, x0
99 isb
100
101 /* ---------------------------------------------
Achin Guptae9c4a642015-09-11 16:03:13 +0100102 * Invalidate the RW memory used by the BL32
103 * image. This includes the data and NOBITS
104 * sections. This is done to safeguard against
105 * possible corruption of this memory by dirty
106 * cache lines in a system cache as a result of
107 * use by an earlier boot loader stage.
108 * ---------------------------------------------
109 */
110 adr x0, __RW_START__
111 adr x1, __RW_END__
112 sub x1, x1, x0
113 bl inv_dcache_range
114
115 /* ---------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000116 * Zero out NOBITS sections. There are 2 of them:
117 * - the .bss section;
118 * - the coherent memory section.
119 * ---------------------------------------------
120 */
121 ldr x0, =__BSS_START__
122 ldr x1, =__BSS_SIZE__
Douglas Raillard21362a92016-12-02 13:51:54 +0000123 bl zeromem
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000124
Soby Mathew2ae20432015-01-08 18:02:44 +0000125#if USE_COHERENT_MEM
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000126 ldr x0, =__COHERENT_RAM_START__
127 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
Douglas Raillard21362a92016-12-02 13:51:54 +0000128 bl zeromem
Soby Mathew2ae20432015-01-08 18:02:44 +0000129#endif
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000130
131 /* --------------------------------------------
Achin Guptaf4a97092014-06-25 19:26:22 +0100132 * Allocate a stack whose memory will be marked
133 * as Normal-IS-WBWA when the MMU is enabled.
134 * There is no risk of reading stale stack
135 * memory after enabling the MMU as only the
136 * primary cpu is running at the moment.
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000137 * --------------------------------------------
138 */
Soby Mathewda43b662015-07-08 21:45:46 +0100139 bl plat_set_my_stack
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000140
141 /* ---------------------------------------------
142 * Perform early platform setup & platform
143 * specific early arch. setup e.g. mmu setup
144 * ---------------------------------------------
145 */
Dan Handley4fd2f5c2014-08-04 11:41:20 +0100146 bl tsp_early_platform_setup
147 bl tsp_plat_arch_setup
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000148
149 /* ---------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000150 * Jump to main function.
151 * ---------------------------------------------
152 */
153 bl tsp_main
154
155 /* ---------------------------------------------
156 * Tell TSPD that we are done initialising
157 * ---------------------------------------------
158 */
159 mov x1, x0
160 mov x0, #TSP_ENTRY_DONE
161 smc #0
162
163tsp_entrypoint_panic:
164 b tsp_entrypoint_panic
Kévin Petita877c252015-03-24 14:03:57 +0000165endfunc tsp_entrypoint
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000166
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100167
168 /* -------------------------------------------
169 * Table of entrypoint vectors provided to the
170 * TSPD for the various entrypoints
171 * -------------------------------------------
172 */
173func tsp_vector_table
174 b tsp_std_smc_entry
175 b tsp_fast_smc_entry
176 b tsp_cpu_on_entry
177 b tsp_cpu_off_entry
178 b tsp_cpu_resume_entry
179 b tsp_cpu_suspend_entry
Soby Mathewbec98512015-09-03 18:29:38 +0100180 b tsp_sel1_intr_entry
Juan Castillo4dc4a472014-08-12 11:17:06 +0100181 b tsp_system_off_entry
182 b tsp_system_reset_entry
Douglas Raillardf2129652016-11-24 15:43:19 +0000183 b tsp_abort_std_smc_entry
Kévin Petita877c252015-03-24 14:03:57 +0000184endfunc tsp_vector_table
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100185
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000186 /*---------------------------------------------
187 * This entrypoint is used by the TSPD when this
188 * cpu is to be turned off through a CPU_OFF
189 * psci call to ask the TSP to perform any
190 * bookeeping necessary. In the current
191 * implementation, the TSPD expects the TSP to
192 * re-initialise its state so nothing is done
193 * here except for acknowledging the request.
194 * ---------------------------------------------
195 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000196func tsp_cpu_off_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000197 bl tsp_cpu_off_main
198 restore_args_call_smc
Kévin Petita877c252015-03-24 14:03:57 +0000199endfunc tsp_cpu_off_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000200
201 /*---------------------------------------------
Juan Castillo4dc4a472014-08-12 11:17:06 +0100202 * This entrypoint is used by the TSPD when the
203 * system is about to be switched off (through
204 * a SYSTEM_OFF psci call) to ask the TSP to
205 * perform any necessary bookkeeping.
206 * ---------------------------------------------
207 */
208func tsp_system_off_entry
209 bl tsp_system_off_main
210 restore_args_call_smc
Kévin Petita877c252015-03-24 14:03:57 +0000211endfunc tsp_system_off_entry
Juan Castillo4dc4a472014-08-12 11:17:06 +0100212
213 /*---------------------------------------------
214 * This entrypoint is used by the TSPD when the
215 * system is about to be reset (through a
216 * SYSTEM_RESET psci call) to ask the TSP to
217 * perform any necessary bookkeeping.
218 * ---------------------------------------------
219 */
220func tsp_system_reset_entry
221 bl tsp_system_reset_main
222 restore_args_call_smc
Kévin Petita877c252015-03-24 14:03:57 +0000223endfunc tsp_system_reset_entry
Juan Castillo4dc4a472014-08-12 11:17:06 +0100224
225 /*---------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000226 * This entrypoint is used by the TSPD when this
227 * cpu is turned on using a CPU_ON psci call to
228 * ask the TSP to initialise itself i.e. setup
229 * the mmu, stacks etc. Minimal architectural
230 * state will be initialised by the TSPD when
231 * this function is entered i.e. Caches and MMU
232 * will be turned off, the execution state
233 * will be aarch64 and exceptions masked.
234 * ---------------------------------------------
235 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000236func tsp_cpu_on_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000237 /* ---------------------------------------------
238 * Set the exception vector to something sane.
239 * ---------------------------------------------
240 */
Achin Guptaa4f50c22014-05-09 12:17:56 +0100241 adr x0, tsp_exceptions
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000242 msr vbar_el1, x0
Achin Guptaed1744e2014-08-04 23:13:10 +0100243 isb
244
245 /* Enable the SError interrupt */
246 msr daifclr, #DAIF_ABT_BIT
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000247
248 /* ---------------------------------------------
Achin Gupta9f098352014-07-18 18:38:28 +0100249 * Enable the instruction cache, stack pointer
250 * and data access alignment checks
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000251 * ---------------------------------------------
252 */
Achin Gupta9f098352014-07-18 18:38:28 +0100253 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000254 mrs x0, sctlr_el1
Achin Gupta9f098352014-07-18 18:38:28 +0100255 orr x0, x0, x1
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000256 msr sctlr_el1, x0
257 isb
258
259 /* --------------------------------------------
Achin Guptae1aa5162014-06-26 09:58:52 +0100260 * Give ourselves a stack whose memory will be
261 * marked as Normal-IS-WBWA when the MMU is
262 * enabled.
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000263 * --------------------------------------------
264 */
Soby Mathewda43b662015-07-08 21:45:46 +0100265 bl plat_set_my_stack
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000266
Achin Guptae1aa5162014-06-26 09:58:52 +0100267 /* --------------------------------------------
268 * Enable the MMU with the DCache disabled. It
269 * is safe to use stacks allocated in normal
270 * memory as a result. All memory accesses are
271 * marked nGnRnE when the MMU is disabled. So
272 * all the stack writes will make it to memory.
273 * All memory accesses are marked Non-cacheable
274 * when the MMU is enabled but D$ is disabled.
275 * So used stack memory is guaranteed to be
276 * visible immediately after the MMU is enabled
277 * Enabling the DCache at the same time as the
278 * MMU can lead to speculatively fetched and
279 * possibly stale stack memory being read from
280 * other caches. This can lead to coherency
281 * issues.
282 * --------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000283 */
Achin Guptae1aa5162014-06-26 09:58:52 +0100284 mov x0, #DISABLE_DCACHE
Dan Handleyb226a4d2014-05-16 14:08:45 +0100285 bl bl32_plat_enable_mmu
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000286
287 /* ---------------------------------------------
Achin Guptae1aa5162014-06-26 09:58:52 +0100288 * Enable the Data cache now that the MMU has
289 * been enabled. The stack has been unwound. It
290 * will be written first before being read. This
291 * will invalidate any stale cache lines resi-
292 * -dent in other caches. We assume that
293 * interconnect coherency has been enabled for
294 * this cluster by EL3 firmware.
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000295 * ---------------------------------------------
296 */
Achin Guptae1aa5162014-06-26 09:58:52 +0100297 mrs x0, sctlr_el1
298 orr x0, x0, #SCTLR_C_BIT
299 msr sctlr_el1, x0
300 isb
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000301
302 /* ---------------------------------------------
303 * Enter C runtime to perform any remaining
304 * book keeping
305 * ---------------------------------------------
306 */
307 bl tsp_cpu_on_main
308 restore_args_call_smc
309
310 /* Should never reach here */
311tsp_cpu_on_entry_panic:
312 b tsp_cpu_on_entry_panic
Kévin Petita877c252015-03-24 14:03:57 +0000313endfunc tsp_cpu_on_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000314
315 /*---------------------------------------------
316 * This entrypoint is used by the TSPD when this
317 * cpu is to be suspended through a CPU_SUSPEND
318 * psci call to ask the TSP to perform any
319 * bookeeping necessary. In the current
320 * implementation, the TSPD saves and restores
321 * the EL1 state.
322 * ---------------------------------------------
323 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000324func tsp_cpu_suspend_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000325 bl tsp_cpu_suspend_main
326 restore_args_call_smc
Kévin Petita877c252015-03-24 14:03:57 +0000327endfunc tsp_cpu_suspend_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000328
Soby Mathewbec98512015-09-03 18:29:38 +0100329 /*-------------------------------------------------
Achin Gupta76717892014-05-09 11:42:56 +0100330 * This entrypoint is used by the TSPD to pass
Soby Mathew78664242015-11-13 02:08:43 +0000331 * control for `synchronously` handling a S-EL1
332 * Interrupt which was triggered while executing
333 * in normal world. 'x0' contains a magic number
334 * which indicates this. TSPD expects control to
335 * be handed back at the end of interrupt
336 * processing. This is done through an SMC.
337 * The handover agreement is:
Achin Gupta76717892014-05-09 11:42:56 +0100338 *
339 * 1. PSTATE.DAIF are set upon entry. 'x1' has
340 * the ELR_EL3 from the non-secure state.
341 * 2. TSP has to preserve the callee saved
342 * general purpose registers, SP_EL1/EL0 and
343 * LR.
344 * 3. TSP has to preserve the system and vfp
345 * registers (if applicable).
346 * 4. TSP can use 'x0-x18' to enable its C
347 * runtime.
348 * 5. TSP returns to TSPD using an SMC with
Soby Mathewbec98512015-09-03 18:29:38 +0100349 * 'x0' = TSP_HANDLED_S_EL1_INTR
350 * ------------------------------------------------
Achin Gupta76717892014-05-09 11:42:56 +0100351 */
Soby Mathewbec98512015-09-03 18:29:38 +0100352func tsp_sel1_intr_entry
Achin Gupta76717892014-05-09 11:42:56 +0100353#if DEBUG
Soby Mathew78664242015-11-13 02:08:43 +0000354 mov_imm x2, TSP_HANDLE_SEL1_INTR_AND_RETURN
Achin Gupta76717892014-05-09 11:42:56 +0100355 cmp x0, x2
Soby Mathewbec98512015-09-03 18:29:38 +0100356 b.ne tsp_sel1_int_entry_panic
Achin Gupta76717892014-05-09 11:42:56 +0100357#endif
Soby Mathewbec98512015-09-03 18:29:38 +0100358 /*-------------------------------------------------
Achin Gupta76717892014-05-09 11:42:56 +0100359 * Save any previous context needed to perform
360 * an exception return from S-EL1 e.g. context
Soby Mathewbec98512015-09-03 18:29:38 +0100361 * from a previous Non secure Interrupt.
362 * Update statistics and handle the S-EL1
363 * interrupt before returning to the TSPD.
Achin Gupta76717892014-05-09 11:42:56 +0100364 * IRQ/FIQs are not enabled since that will
365 * complicate the implementation. Execution
366 * will be transferred back to the normal world
Soby Mathew78664242015-11-13 02:08:43 +0000367 * in any case. The handler can return 0
368 * if the interrupt was handled or TSP_PREEMPTED
369 * if the expected interrupt was preempted
370 * by an interrupt that should be handled in EL3
371 * e.g. Group 0 interrupt in GICv3. In both
372 * the cases switch to EL3 using SMC with id
373 * TSP_HANDLED_S_EL1_INTR. Any other return value
374 * from the handler will result in panic.
Soby Mathewbec98512015-09-03 18:29:38 +0100375 * ------------------------------------------------
Achin Gupta76717892014-05-09 11:42:56 +0100376 */
377 save_eret_context x2 x3
Soby Mathewbec98512015-09-03 18:29:38 +0100378 bl tsp_update_sync_sel1_intr_stats
379 bl tsp_common_int_handler
Soby Mathew78664242015-11-13 02:08:43 +0000380 /* Check if the S-EL1 interrupt has been handled */
381 cbnz x0, tsp_sel1_intr_check_preemption
382 b tsp_sel1_intr_return
383tsp_sel1_intr_check_preemption:
384 /* Check if the S-EL1 interrupt has been preempted */
385 mov_imm x1, TSP_PREEMPTED
386 cmp x0, x1
387 b.ne tsp_sel1_int_entry_panic
388tsp_sel1_intr_return:
389 mov_imm x0, TSP_HANDLED_S_EL1_INTR
Achin Gupta76717892014-05-09 11:42:56 +0100390 restore_eret_context x2 x3
Achin Gupta76717892014-05-09 11:42:56 +0100391 smc #0
392
Soby Mathew78664242015-11-13 02:08:43 +0000393 /* Should never reach here */
Soby Mathewbec98512015-09-03 18:29:38 +0100394tsp_sel1_int_entry_panic:
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000395 no_ret plat_panic_handler
Soby Mathewbec98512015-09-03 18:29:38 +0100396endfunc tsp_sel1_intr_entry
Achin Gupta76717892014-05-09 11:42:56 +0100397
398 /*---------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000399 * This entrypoint is used by the TSPD when this
400 * cpu resumes execution after an earlier
401 * CPU_SUSPEND psci call to ask the TSP to
402 * restore its saved context. In the current
403 * implementation, the TSPD saves and restores
404 * EL1 state so nothing is done here apart from
405 * acknowledging the request.
406 * ---------------------------------------------
407 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000408func tsp_cpu_resume_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000409 bl tsp_cpu_resume_main
410 restore_args_call_smc
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000411
412 /* Should never reach here */
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000413 no_ret plat_panic_handler
Kévin Petita877c252015-03-24 14:03:57 +0000414endfunc tsp_cpu_resume_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000415
416 /*---------------------------------------------
417 * This entrypoint is used by the TSPD to ask
418 * the TSP to service a fast smc request.
419 * ---------------------------------------------
420 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000421func tsp_fast_smc_entry
Soby Mathew9f71f702014-05-09 20:49:17 +0100422 bl tsp_smc_handler
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000423 restore_args_call_smc
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000424
425 /* Should never reach here */
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000426 no_ret plat_panic_handler
Kévin Petita877c252015-03-24 14:03:57 +0000427endfunc tsp_fast_smc_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000428
Soby Mathew9f71f702014-05-09 20:49:17 +0100429 /*---------------------------------------------
430 * This entrypoint is used by the TSPD to ask
431 * the TSP to service a std smc request.
432 * We will enable preemption during execution
433 * of tsp_smc_handler.
434 * ---------------------------------------------
435 */
436func tsp_std_smc_entry
437 msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT
438 bl tsp_smc_handler
439 msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT
440 restore_args_call_smc
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000441
442 /* Should never reach here */
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000443 no_ret plat_panic_handler
Kévin Petita877c252015-03-24 14:03:57 +0000444endfunc tsp_std_smc_entry
Douglas Raillardf2129652016-11-24 15:43:19 +0000445
446 /*---------------------------------------------------------------------
447 * This entrypoint is used by the TSPD to abort a pre-empted Standard
448 * SMC. It could be on behalf of non-secure world or because a CPU
449 * suspend/CPU off request needs to abort the preempted SMC.
450 * --------------------------------------------------------------------
451 */
452func tsp_abort_std_smc_entry
453
454 /*
455 * Exceptions masking is already done by the TSPD when entering this
456 * hook so there is no need to do it here.
457 */
458
459 /* Reset the stack used by the pre-empted SMC */
460 bl plat_set_my_stack
461
462 /*
463 * Allow some cleanup such as releasing locks.
464 */
465 bl tsp_abort_smc_handler
466
467 restore_args_call_smc
468
469 /* Should never reach here */
470 bl plat_panic_handler
471endfunc tsp_abort_std_smc_entry