David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 1 | /* |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 9 | #include <cortex_a75.h> |
Dimitris Papastamos | 1be747f | 2018-02-14 10:28:36 +0000 | [diff] [blame] | 10 | #include <cpuamu.h> |
| 11 | #include <cpu_macros.S> |
Dimitris Papastamos | d7e2e9e | 2017-12-11 11:45:35 +0000 | [diff] [blame] | 12 | |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 13 | func cortex_a75_reset_func |
Dimitris Papastamos | c52ebdc | 2017-12-18 13:46:21 +0000 | [diff] [blame] | 14 | #if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 |
Dimitris Papastamos | 780cc95 | 2018-03-12 13:27:02 +0000 | [diff] [blame] | 15 | cpu_check_csv2 x0, 1f |
Dimitris Papastamos | c52ebdc | 2017-12-18 13:46:21 +0000 | [diff] [blame] | 16 | adr x0, workaround_bpiall_vbar0_runtime_exceptions |
| 17 | msr vbar_el3, x0 |
Dimitris Papastamos | 43e05ec | 2018-01-02 15:53:01 +0000 | [diff] [blame] | 18 | 1: |
Dimitris Papastamos | c52ebdc | 2017-12-18 13:46:21 +0000 | [diff] [blame] | 19 | #endif |
| 20 | |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 21 | #if ENABLE_AMU |
| 22 | /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ |
| 23 | mrs x0, actlr_el3 |
| 24 | orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT |
| 25 | msr actlr_el3, x0 |
| 26 | isb |
| 27 | |
| 28 | /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ |
| 29 | mrs x0, actlr_el2 |
| 30 | orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT |
| 31 | msr actlr_el2, x0 |
| 32 | isb |
| 33 | |
| 34 | /* Enable group0 counters */ |
| 35 | mov x0, #CORTEX_A75_AMU_GROUP0_MASK |
| 36 | msr CPUAMCNTENSET_EL0, x0 |
| 37 | isb |
| 38 | |
| 39 | /* Enable group1 counters */ |
| 40 | mov x0, #CORTEX_A75_AMU_GROUP1_MASK |
| 41 | msr CPUAMCNTENSET_EL0, x0 |
| 42 | isb |
| 43 | #endif |
| 44 | ret |
| 45 | endfunc cortex_a75_reset_func |
| 46 | |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 47 | func check_errata_cve_2017_5715 |
Dimitris Papastamos | 780cc95 | 2018-03-12 13:27:02 +0000 | [diff] [blame] | 48 | cpu_check_csv2 x0, 1f |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 49 | #if WORKAROUND_CVE_2017_5715 |
| 50 | mov x0, #ERRATA_APPLIES |
| 51 | #else |
| 52 | mov x0, #ERRATA_MISSING |
| 53 | #endif |
| 54 | ret |
| 55 | 1: |
| 56 | mov x0, #ERRATA_NOT_APPLIES |
| 57 | ret |
| 58 | endfunc check_errata_cve_2017_5715 |
| 59 | |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 60 | /* --------------------------------------------- |
| 61 | * HW will do the cache maintenance while powering down |
| 62 | * --------------------------------------------- |
| 63 | */ |
| 64 | func cortex_a75_core_pwr_dwn |
| 65 | /* --------------------------------------------- |
| 66 | * Enable CPU power down bit in power control register |
| 67 | * --------------------------------------------- |
| 68 | */ |
| 69 | mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 |
| 70 | orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK |
| 71 | msr CORTEX_A75_CPUPWRCTLR_EL1, x0 |
| 72 | isb |
| 73 | ret |
| 74 | endfunc cortex_a75_core_pwr_dwn |
| 75 | |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 76 | #if REPORT_ERRATA |
| 77 | /* |
| 78 | * Errata printing function for Cortex A75. Must follow AAPCS. |
| 79 | */ |
| 80 | func cortex_a75_errata_report |
| 81 | stp x8, x30, [sp, #-16]! |
| 82 | |
| 83 | bl cpu_get_rev_var |
| 84 | mov x8, x0 |
| 85 | |
| 86 | /* |
| 87 | * Report all errata. The revision-variant information is passed to |
| 88 | * checking functions of each errata. |
| 89 | */ |
| 90 | report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715 |
| 91 | |
| 92 | ldp x8, x30, [sp], #16 |
| 93 | ret |
| 94 | endfunc cortex_a75_errata_report |
| 95 | #endif |
| 96 | |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 97 | /* --------------------------------------------- |
| 98 | * This function provides cortex_a75 specific |
| 99 | * register information for crash reporting. |
| 100 | * It needs to return with x6 pointing to |
| 101 | * a list of register names in ascii and |
| 102 | * x8 - x15 having values of registers to be |
| 103 | * reported. |
| 104 | * --------------------------------------------- |
| 105 | */ |
| 106 | .section .rodata.cortex_a75_regs, "aS" |
| 107 | cortex_a75_regs: /* The ascii list of register names to be reported */ |
| 108 | .asciz "cpuectlr_el1", "" |
| 109 | |
| 110 | func cortex_a75_cpu_reg_dump |
| 111 | adr x6, cortex_a75_regs |
| 112 | mrs x8, CORTEX_A75_CPUECTLR_EL1 |
| 113 | ret |
| 114 | endfunc cortex_a75_cpu_reg_dump |
| 115 | |
Dimitris Papastamos | 914757c | 2018-03-12 14:47:09 +0000 | [diff] [blame] | 116 | declare_cpu_ops_workaround_cve_2017_5715 cortex_a75, CORTEX_A75_MIDR, \ |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 117 | cortex_a75_reset_func, \ |
Dimitris Papastamos | 914757c | 2018-03-12 14:47:09 +0000 | [diff] [blame] | 118 | check_errata_cve_2017_5715, \ |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 119 | cortex_a75_core_pwr_dwn |