Hadi Asyrafi | 5fae68f | 2019-10-22 14:23:57 +0800 | [diff] [blame] | 1 | /* |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. |
Hadi Asyrafi | 5fae68f | 2019-10-22 14:23:57 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SOCFPGA_RESETMANAGER_H |
| 8 | #define SOCFPGA_RESETMANAGER_H |
| 9 | |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 10 | #include "socfpga_plat_def.h" |
| 11 | |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 12 | /* Status Response */ |
| 13 | #define RSTMGR_RET_OK 0 |
| 14 | #define RSTMGR_RET_ERROR -1 |
| 15 | |
Sieu Mun Tang | 044ed48 | 2022-05-11 10:45:19 +0800 | [diff] [blame] | 16 | #define SOCFPGA_BRIDGE_ENABLE BIT(0) |
| 17 | #define SOCFPGA_BRIDGE_HAS_MASK BIT(1) |
Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 18 | |
Sieu Mun Tang | 044ed48 | 2022-05-11 10:45:19 +0800 | [diff] [blame] | 19 | #define SOC2FPGA_MASK (1<<0) |
| 20 | #define LWHPS2FPGA_MASK (1<<1) |
| 21 | #define FPGA2SOC_MASK (1<<2) |
| 22 | #define F2SDRAM0_MASK (1<<3) |
| 23 | #define F2SDRAM1_MASK (1<<4) |
| 24 | #define F2SDRAM2_MASK (1<<5) |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 25 | |
| 26 | /* Register Mapping */ |
| 27 | |
| 28 | #define SOCFPGA_RSTMGR_STAT 0x000 |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 29 | #define SOCFPGA_RSTMGR_MISCSTAT 0x008 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 30 | #define SOCFPGA_RSTMGR_HDSKEN 0x010 |
Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 31 | #define SOCFPGA_RSTMGR_HDSKREQ 0x014 |
| 32 | #define SOCFPGA_RSTMGR_HDSKACK 0x018 |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 33 | #define SOCFPGA_RSTMGR_HDSKSTALL 0x01C |
| 34 | #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 35 | #define SOCFPGA_RSTMGR_MPUMODRST 0x020 |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 36 | #endif |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 37 | #define SOCFPGA_RSTMGR_PER0MODRST 0x024 |
| 38 | #define SOCFPGA_RSTMGR_PER1MODRST 0x028 |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 39 | #define SOCFPGA_RSTMGR_BRGMODRST 0x02C |
| 40 | #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 41 | #define SOCFPGA_RSTMGR_COLDMODRST 0x034 |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 42 | #endif |
| 43 | #define SOCFPGA_RSTMGR_DBGMODRST 0x03C |
| 44 | #define SOCFPGA_RSTMGR_BRGWARMMASK 0x04C |
| 45 | #define SOCFPGA_RSTMGR_TSTSTA 0x05C |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 46 | #define SOCFPGA_RSTMGR_HDSKTIMEOUT 0x064 |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 47 | #define SOCFPGA_RSTMGR_DBGHDSKTIMEOUT 0x06C |
| 48 | #define SOCFPGA_RSTMGR_DBGRSTCMPLT 0x070 |
| 49 | #define SOCFPGA_RSTMGR_HPSRSTCMPLT 0x080 |
| 50 | #define SOCFPGA_RSTMGR_CPUINREST 0x090 |
| 51 | #define SOCFPGA_RSTMGR_CPURSTRELEASE 0x094 |
| 52 | #define SOCFPGA_RSTMGR_CPUBASELOW_0 0x098 |
| 53 | #define SOCFPGA_RSTMGR_CPUBASEHIGH_0 0x09C |
| 54 | #define SOCFPGA_RSTMGR_CPUBASELOW_1 0x0A0 |
| 55 | #define SOCFPGA_RSTMGR_CPUBASEHIGH_1 0x0A4 |
| 56 | #define SOCFPGA_RSTMGR_CPUBASELOW_2 0x0A8 |
| 57 | #define SOCFPGA_RSTMGR_CPUBASEHIGH_2 0x0AC |
| 58 | #define SOCFPGA_RSTMGR_CPUBASELOW_3 0x0B0 |
| 59 | #define SOCFPGA_RSTMGR_CPUBASEHIGH_3 0x0B4 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 60 | |
| 61 | /* Field Mapping */ |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 62 | /* PER0MODRST */ |
| 63 | #define RSTMGR_PER0MODRST_EMAC0 0x00000001 //TSN0 |
| 64 | #define RSTMGR_PER0MODRST_EMAC1 0x00000002 //TSN1 |
| 65 | #define RSTMGR_PER0MODRST_EMAC2 0x00000004 //TSN2 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 66 | #define RSTMGR_PER0MODRST_USB0 0x00000008 |
| 67 | #define RSTMGR_PER0MODRST_USB1 0x00000010 |
| 68 | #define RSTMGR_PER0MODRST_NAND 0x00000020 |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 69 | #define RSTMGR_PER0MODRST_SOFTPHY 0x00000040 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 70 | #define RSTMGR_PER0MODRST_SDMMC 0x00000080 |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 71 | #define RSTMGR_PER0MODRST_EMAC0OCP 0x00000100 //TSN0ECC |
| 72 | #define RSTMGR_PER0MODRST_EMAC1OCP 0x00000200 //TSN1ECC |
| 73 | #define RSTMGR_PER0MODRST_EMAC2OCP 0x00000400 //TSN2ECC |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 74 | #define RSTMGR_PER0MODRST_USB0OCP 0x00000800 |
| 75 | #define RSTMGR_PER0MODRST_USB1OCP 0x00001000 |
| 76 | #define RSTMGR_PER0MODRST_NANDOCP 0x00002000 |
| 77 | #define RSTMGR_PER0MODRST_SDMMCOCP 0x00008000 |
| 78 | #define RSTMGR_PER0MODRST_DMA 0x00010000 |
| 79 | #define RSTMGR_PER0MODRST_SPIM0 0x00020000 |
| 80 | #define RSTMGR_PER0MODRST_SPIM1 0x00040000 |
| 81 | #define RSTMGR_PER0MODRST_SPIS0 0x00080000 |
| 82 | #define RSTMGR_PER0MODRST_SPIS1 0x00100000 |
| 83 | #define RSTMGR_PER0MODRST_DMAOCP 0x00200000 |
| 84 | #define RSTMGR_PER0MODRST_EMACPTP 0x00400000 |
| 85 | #define RSTMGR_PER0MODRST_DMAIF0 0x01000000 |
| 86 | #define RSTMGR_PER0MODRST_DMAIF1 0x02000000 |
| 87 | #define RSTMGR_PER0MODRST_DMAIF2 0x04000000 |
| 88 | #define RSTMGR_PER0MODRST_DMAIF3 0x08000000 |
| 89 | #define RSTMGR_PER0MODRST_DMAIF4 0x10000000 |
| 90 | #define RSTMGR_PER0MODRST_DMAIF5 0x20000000 |
| 91 | #define RSTMGR_PER0MODRST_DMAIF6 0x40000000 |
| 92 | #define RSTMGR_PER0MODRST_DMAIF7 0x80000000 |
| 93 | |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 94 | /* PER1MODRST */ |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 95 | #define RSTMGR_PER1MODRST_WATCHDOG0 0x00000001 |
| 96 | #define RSTMGR_PER1MODRST_WATCHDOG1 0x00000002 |
| 97 | #define RSTMGR_PER1MODRST_WATCHDOG2 0x00000004 |
| 98 | #define RSTMGR_PER1MODRST_WATCHDOG3 0x00000008 |
| 99 | #define RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010 |
| 100 | #define RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020 |
| 101 | #define RSTMGR_PER1MODRST_SPTIMER0 0x00000040 |
| 102 | #define RSTMGR_PER1MODRST_SPTIMER1 0x00000080 |
| 103 | #define RSTMGR_PER1MODRST_I2C0 0x00000100 |
| 104 | #define RSTMGR_PER1MODRST_I2C1 0x00000200 |
| 105 | #define RSTMGR_PER1MODRST_I2C2 0x00000400 |
| 106 | #define RSTMGR_PER1MODRST_I2C3 0x00000800 |
| 107 | #define RSTMGR_PER1MODRST_I2C4 0x00001000 |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 108 | #define RSTMGR_PER1MODRST_I3C0 0x00002000 |
| 109 | #define RSTMGR_PER1MODRST_I3C1 0x00004000 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 110 | #define RSTMGR_PER1MODRST_UART0 0x00010000 |
| 111 | #define RSTMGR_PER1MODRST_UART1 0x00020000 |
| 112 | #define RSTMGR_PER1MODRST_GPIO0 0x01000000 |
| 113 | #define RSTMGR_PER1MODRST_GPIO1 0x02000000 |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 114 | #define RSTMGR_PER1MODRST_WATCHDOG4 0x04000000 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 115 | |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 116 | /* HDSKEN */ |
| 117 | #define RSTMGR_HDSKEN_EMIF_FLUSH 0x00000001 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 118 | #define RSTMGR_HDSKEN_FPGAHSEN 0x00000004 |
| 119 | #define RSTMGR_HDSKEN_ETRSTALLEN 0x00000008 |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 120 | #define RSTMGR_HDSKEN_LWS2F_FLUSH 0x00000200 |
| 121 | #define RSTMGR_HDSKEN_S2F_FLUSH 0x00000400 |
| 122 | #define RSTMGR_HDSKEN_F2SDRAM_FLUSH 0x00000800 |
| 123 | #define RSTMGR_HDSKEN_F2S_FLUSH 0x00001000 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 124 | #define RSTMGR_HDSKEN_L3NOC_DBG 0x00010000 |
| 125 | #define RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 126 | |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 127 | /* HDSKREQ */ |
| 128 | #define RSTMGR_HDSKREQ_EMIFFLUSHREQ 0x00000001 |
| 129 | #define RSTMGR_HDSKREQ_ETRSTALLREQ 0x00000008 |
| 130 | #define RSTMGR_HDSKREQ_LWS2F_FLUSH 0x00000200 |
| 131 | #define RSTMGR_HDSKREQ_S2F_FLUSH 0x00000400 |
| 132 | #define RSTMGR_HDSKREQ_F2SDRAM_FLUSH 0x00000800 |
| 133 | #define RSTMGR_HDSKREQ_F2S_FLUSH 0x00001000 |
| 134 | #define RSTMGR_HDSKREQ_L3NOC_DBG 0x00010000 |
| 135 | #define RSTMGR_HDSKREQ_DEBUG_L3NOC 0x00020000 |
| 136 | #define RSTMGR_HDSKREQ_FPGAHSREQ 0x00000004 |
| 137 | #define RSTMGR_HDSKREQ_LWSOC2FPGAREQ 0x00000200 |
| 138 | #define RSTMGR_HDSKREQ_SOC2FPGAREQ 0x00000400 |
| 139 | #define RSTMGR_HDSKREQ_F2SDRAM0REQ 0x00000800 |
| 140 | #define RSTMGR_HDSKREQ_FPGA2SOCREQ 0x00001000 |
Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 141 | |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 142 | /* HDSKACK */ |
| 143 | #define RSTMGR_HDSKACK_EMIFFLUSHREQ 0x00000001 |
| 144 | #define RSTMGR_HDSKACK_FPGAHSREQ 0x00000004 |
| 145 | #define RSTMGR_HDSKACK_ETRSTALLREQ 0x00000008 |
| 146 | #define RSTMGR_HDSKACK_LWS2F_FLUSH 0x00000200 |
| 147 | #define RSTMGR_HDSKACK_S2F_FLUSH 0x00000400 |
| 148 | #define RSTMGR_HDSKACK_F2SDRAM_FLUSH 0x00000800 |
| 149 | #define RSTMGR_HDSKACK_F2S_FLUSH 0x00001000 |
| 150 | #define RSTMGR_HDSKACK_L3NOC_DBG 0x00010000 |
| 151 | #define RSTMGR_HDSKACK_DEBUG_L3NOC 0x00020000 |
| 152 | #define RSTMGR_HDSKACK_FPGAHSACK 0x00000004 |
| 153 | #define RSTMGR_HDSKACK_LWSOC2FPGAACK 0x00000200 |
| 154 | #define RSTMGR_HDSKACK_SOC2FPGAACK 0x00000400 |
| 155 | #define RSTMGR_HDSKACK_F2SDRAM0ACK 0x00000800 |
| 156 | #define RSTMGR_HDSKACK_FPGA2SOCACK 0x00001000 |
| 157 | #define RSTMGR_HDSKACK_FPGAHSACK_DASRT 0x00000000 |
| 158 | #define RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT 0x00000000 |
| 159 | #define RSTMGR_HDSKACK_FPGA2SOCACK_DASRT 0x00000000 |
| 160 | |
| 161 | /* HDSKSTALL */ |
| 162 | #define RSTMGR_HDSKACK_ETRSTALLWARMRST 0x00000001 |
| 163 | |
| 164 | /* BRGMODRST */ |
| 165 | #define RSTMGR_BRGMODRST_SOC2FPGA 0x00000001 |
| 166 | #define RSTMGR_BRGMODRST_LWHPS2FPGA 0x00000002 |
| 167 | #define RSTMGR_BRGMODRST_FPGA2SOC 0x00000004 |
| 168 | #define RSTMGR_BRGMODRST_F2SSDRAM0 0x00000008 |
| 169 | #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 170 | #define RSTMGR_BRGMODRST_F2SSDRAM1 0x10 |
| 171 | #define RSTMGR_BRGMODRST_F2SSDRAM2 0x20 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 172 | #define RSTMGR_BRGMODRST_DDRSCH 0x40 |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 173 | #elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 |
| 174 | #define RSTMGR_BRGMODRST_F2SSDRAM1 0x10 |
| 175 | #define RSTMGR_BRGMODRST_F2SSDRAM2 0x20 |
| 176 | #endif |
| 177 | |
| 178 | #define RSTMGR_BRGMODRST_MPFE 0x40 |
| 179 | |
| 180 | /* DBGMODRST */ |
| 181 | #define RSTMGR_DBGMODRST_DBG_RST 0x00000001 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 182 | |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 183 | /* BRGMODRSTMASK */ |
| 184 | #define RSTMGR_BRGMODRSTMASK_SOC2FPGA 0x00000001 |
| 185 | #define RSTMGR_BRGMODRSTMASK_LWHPS2FPGA 0x00000002 |
| 186 | #define RSTMGR_BRGMODRSTMASK_FPGA2SOC 0x00000004 |
| 187 | #define RSTMGR_BRGMODRSTMASK_F2SDRAM0 0x00000008 |
| 188 | #define RSTMGR_BRGMODRSTMASK_MPFE 0x00000040 |
| 189 | |
| 190 | /* TSTSTA */ |
| 191 | #define RSTMGR_TSTSTA_RSTST 0x0000001F |
| 192 | |
| 193 | /* HDSKTIMEOUT */ |
| 194 | #define RSTMGR_HDSKTIMEOUT_VAL 0xFFFFFFFF |
| 195 | |
| 196 | /* DBGHDSKTIMEOUT */ |
| 197 | #define RSTMGR_DBGHDSKTIMEOUT_VAL 0xFFFFFFFF |
| 198 | |
| 199 | /* DBGRSTCMPLT */ |
| 200 | #define RSTMGR_DBGRSTCMPLT_VAL 0xFFFFFFFF |
| 201 | |
| 202 | /* HPSRSTCMPLT */ |
| 203 | #define RSTMGR_DBGRSTCMPLT_VAL 0xFFFFFFFF |
| 204 | |
| 205 | /* CPUINRESET */ |
| 206 | #define RSTMGR_CPUINRESET_CPU0 0x00000001 |
| 207 | #define RSTMGR_CPUINRESET_CPU1 0x00000002 |
| 208 | #define RSTMGR_CPUINRESET_CPU2 0x00000004 |
| 209 | #define RSTMGR_CPUINRESET_CPU3 0x00000008 |
| 210 | |
| 211 | /* CPUSTRELEASE */ |
| 212 | #define RSTMGR_CPUSTRELEASE_CPUx 0x10D11094 |
| 213 | |
| 214 | /* CPUxRESETBASE */ |
| 215 | #define RSTMGR_CPUxRESETBASELOW_CPU0 0x10D11098 |
| 216 | #define RSTMGR_CPUxRESETBASEHIGH_CPU0 0x10D1109C |
| 217 | #define RSTMGR_CPUxRESETBASELOW_CPU1 0x10D110A0 |
| 218 | #define RSTMGR_CPUxRESETBASEHIGH_CPU1 0x10D110A4 |
| 219 | #define RSTMGR_CPUxRESETBASELOW_CPU2 0x10D110A8 |
| 220 | #define RSTMGR_CPUxRESETBASEHIGH_CPU2 0x10D110AC |
| 221 | #define RSTMGR_CPUxRESETBASELOW_CPU3 0x10D110B0 |
| 222 | #define RSTMGR_CPUxRESETBASEHIGH_CPU3 0x10D110B4 |
Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 223 | |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 224 | /* Definitions */ |
| 225 | |
| 226 | #define RSTMGR_L2_MODRST 0x0100 |
| 227 | #define RSTMGR_HDSKEN_SET 0x010D |
| 228 | |
| 229 | /* Macros */ |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 230 | #define SOCFPGA_RSTMGR(_reg) (SOCFPGA_RSTMGR_REG_BASE + (SOCFPGA_RSTMGR_##_reg)) |
| 231 | #define RSTMGR_FIELD(_reg, _field) (RSTMGR_##_reg##MODRST_##_field) |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 232 | |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 233 | /* Reset type to SDM from PSCI */ |
| 234 | // Temp add macro here for reset type |
| 235 | #define SOCFPGA_RESET_TYPE_COLD 0 |
| 236 | #define SOCFPGA_RESET_TYPE_WARM 1 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 237 | |
| 238 | /* Function Declarations */ |
| 239 | |
| 240 | void deassert_peripheral_reset(void); |
| 241 | void config_hps_hs_before_warm_reset(void); |
Hadi Asyrafi | 5fae68f | 2019-10-22 14:23:57 +0800 | [diff] [blame] | 242 | |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 243 | int socfpga_bridges_reset(uint32_t mask); |
Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 244 | int socfpga_bridges_enable(uint32_t mask); |
| 245 | int socfpga_bridges_disable(uint32_t mask); |
Hadi Asyrafi | 5fae68f | 2019-10-22 14:23:57 +0800 | [diff] [blame] | 246 | |
Jit Loon Lim | 86733dd | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 247 | int socfpga_cpurstrelease(unsigned int cpu_id); |
| 248 | int socfpga_cpu_reset_base(unsigned int cpu_id); |
| 249 | |
| 250 | /* SMP: Func proto */ |
| 251 | void bl31_plat_set_secondary_cpu_entrypoint(unsigned int cpu_id); |
| 252 | void bl31_plat_set_secondary_cpu_off(void); |
| 253 | |
Hadi Asyrafi | 5fae68f | 2019-10-22 14:23:57 +0800 | [diff] [blame] | 254 | #endif /* SOCFPGA_RESETMANAGER_H */ |