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Achin Gupta7c88f3f2014-02-18 18:09:12 +00001/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta7c88f3f2014-02-18 18:09:12 +000031#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010032#include <bl_common.h>
Achin Gupta7c88f3f2014-02-18 18:09:12 +000033#include <debug.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010034#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010035#include <platform_def.h>
Dan Handley4fd2f5c2014-08-04 11:41:20 +010036#include <platform_tsp.h>
Achin Gupta7c88f3f2014-02-18 18:09:12 +000037#include <spinlock.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010038#include <tsp.h>
Dan Handleye2c27f52014-08-01 17:58:27 +010039#include "tsp_private.h"
Achin Gupta7c88f3f2014-02-18 18:09:12 +000040
Vikram Kanigirid8c9d262014-05-16 18:48:12 +010041
42/*******************************************************************************
Achin Gupta7c88f3f2014-02-18 18:09:12 +000043 * Lock to control access to the console
44 ******************************************************************************/
45spinlock_t console_lock;
46
47/*******************************************************************************
48 * Per cpu data structure to populate parameters for an SMC in C code and use
49 * a pointer to this structure in assembler code to populate x0-x7
50 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +010051static tsp_args_t tsp_smc_args[PLATFORM_CORE_COUNT];
Achin Gupta7c88f3f2014-02-18 18:09:12 +000052
53/*******************************************************************************
54 * Per cpu data structure to keep track of TSP activity
55 ******************************************************************************/
Achin Gupta76717892014-05-09 11:42:56 +010056work_statistics_t tsp_stats[PLATFORM_CORE_COUNT];
Achin Gupta7c88f3f2014-02-18 18:09:12 +000057
58/*******************************************************************************
Vikram Kanigirid8c9d262014-05-16 18:48:12 +010059 * The BL32 memory footprint starts with an RO sections and ends
Soby Mathew2ae20432015-01-08 18:02:44 +000060 * with the linker symbol __BL32_END__. Use it to find the memory size
Vikram Kanigirid8c9d262014-05-16 18:48:12 +010061 ******************************************************************************/
62#define BL32_TOTAL_BASE (unsigned long)(&__RO_START__)
63
Soby Mathew2ae20432015-01-08 18:02:44 +000064#define BL32_TOTAL_LIMIT (unsigned long)(&__BL32_END__)
Vikram Kanigirid8c9d262014-05-16 18:48:12 +010065
Dan Handleye2712bc2014-04-10 15:37:22 +010066static tsp_args_t *set_smc_args(uint64_t arg0,
Achin Gupta7c88f3f2014-02-18 18:09:12 +000067 uint64_t arg1,
68 uint64_t arg2,
69 uint64_t arg3,
70 uint64_t arg4,
71 uint64_t arg5,
72 uint64_t arg6,
73 uint64_t arg7)
74{
75 uint64_t mpidr = read_mpidr();
76 uint32_t linear_id;
Dan Handleye2712bc2014-04-10 15:37:22 +010077 tsp_args_t *pcpu_smc_args;
Achin Gupta7c88f3f2014-02-18 18:09:12 +000078
79 /*
80 * Return to Secure Monitor by raising an SMC. The results of the
81 * service are passed as an arguments to the SMC
82 */
83 linear_id = platform_get_core_pos(mpidr);
84 pcpu_smc_args = &tsp_smc_args[linear_id];
85 write_sp_arg(pcpu_smc_args, TSP_ARG0, arg0);
86 write_sp_arg(pcpu_smc_args, TSP_ARG1, arg1);
87 write_sp_arg(pcpu_smc_args, TSP_ARG2, arg2);
88 write_sp_arg(pcpu_smc_args, TSP_ARG3, arg3);
89 write_sp_arg(pcpu_smc_args, TSP_ARG4, arg4);
90 write_sp_arg(pcpu_smc_args, TSP_ARG5, arg5);
91 write_sp_arg(pcpu_smc_args, TSP_ARG6, arg6);
92 write_sp_arg(pcpu_smc_args, TSP_ARG7, arg7);
93
94 return pcpu_smc_args;
95}
96
97/*******************************************************************************
98 * TSP main entry point where it gets the opportunity to initialize its secure
99 * state/applications. Once the state is initialized, it must return to the
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100100 * SPD with a pointer to the 'tsp_vector_table' jump table.
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000101 ******************************************************************************/
102uint64_t tsp_main(void)
103{
Dan Handley91b624e2014-07-29 17:14:00 +0100104 NOTICE("TSP: %s\n", version_string);
105 NOTICE("TSP: %s\n", build_message);
Sandrine Bailleux8723adf2015-02-05 15:42:31 +0000106 INFO("TSP: Total memory base : 0x%lx\n", BL32_TOTAL_BASE);
107 INFO("TSP: Total memory size : 0x%lx bytes\n",
108 BL32_TOTAL_LIMIT - BL32_TOTAL_BASE);
Dan Handley91b624e2014-07-29 17:14:00 +0100109
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000110 uint64_t mpidr = read_mpidr();
111 uint32_t linear_id = platform_get_core_pos(mpidr);
112
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000113 /* Initialize the platform */
Dan Handley4fd2f5c2014-08-04 11:41:20 +0100114 tsp_platform_setup();
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000115
116 /* Initialize secure/applications state here */
Achin Guptabbc33f22014-05-09 13:33:42 +0100117 tsp_generic_timer_start();
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000118
119 /* Update this cpu's statistics */
120 tsp_stats[linear_id].smc_count++;
121 tsp_stats[linear_id].eret_count++;
122 tsp_stats[linear_id].cpu_on_count++;
123
Dan Handley91b624e2014-07-29 17:14:00 +0100124#if LOG_LEVEL >= LOG_LEVEL_INFO
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000125 spin_lock(&console_lock);
Sandrine Bailleux8723adf2015-02-05 15:42:31 +0000126 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", mpidr,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000127 tsp_stats[linear_id].smc_count,
128 tsp_stats[linear_id].eret_count,
129 tsp_stats[linear_id].cpu_on_count);
130 spin_unlock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +0100131#endif
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100132 return (uint64_t) &tsp_vector_table;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000133}
134
135/*******************************************************************************
136 * This function performs any remaining book keeping in the test secure payload
137 * after this cpu's architectural state has been setup in response to an earlier
138 * psci cpu_on request.
139 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100140tsp_args_t *tsp_cpu_on_main(void)
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000141{
142 uint64_t mpidr = read_mpidr();
143 uint32_t linear_id = platform_get_core_pos(mpidr);
144
Achin Guptabbc33f22014-05-09 13:33:42 +0100145 /* Initialize secure/applications state here */
146 tsp_generic_timer_start();
147
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000148 /* Update this cpu's statistics */
149 tsp_stats[linear_id].smc_count++;
150 tsp_stats[linear_id].eret_count++;
151 tsp_stats[linear_id].cpu_on_count++;
152
Dan Handley91b624e2014-07-29 17:14:00 +0100153#if LOG_LEVEL >= LOG_LEVEL_INFO
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000154 spin_lock(&console_lock);
Sandrine Bailleux8723adf2015-02-05 15:42:31 +0000155 INFO("TSP: cpu 0x%lx turned on\n", mpidr);
156 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", mpidr,
Dan Handley91b624e2014-07-29 17:14:00 +0100157 tsp_stats[linear_id].smc_count,
158 tsp_stats[linear_id].eret_count,
159 tsp_stats[linear_id].cpu_on_count);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000160 spin_unlock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +0100161#endif
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000162 /* Indicate to the SPD that we have completed turned ourselves on */
163 return set_smc_args(TSP_ON_DONE, 0, 0, 0, 0, 0, 0, 0);
164}
165
166/*******************************************************************************
167 * This function performs any remaining book keeping in the test secure payload
168 * before this cpu is turned off in response to a psci cpu_off request.
169 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100170tsp_args_t *tsp_cpu_off_main(uint64_t arg0,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000171 uint64_t arg1,
172 uint64_t arg2,
173 uint64_t arg3,
174 uint64_t arg4,
175 uint64_t arg5,
176 uint64_t arg6,
177 uint64_t arg7)
178{
179 uint64_t mpidr = read_mpidr();
180 uint32_t linear_id = platform_get_core_pos(mpidr);
181
Achin Guptabbc33f22014-05-09 13:33:42 +0100182 /*
183 * This cpu is being turned off, so disable the timer to prevent the
184 * secure timer interrupt from interfering with power down. A pending
185 * interrupt will be lost but we do not care as we are turning off.
186 */
187 tsp_generic_timer_stop();
188
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000189 /* Update this cpu's statistics */
190 tsp_stats[linear_id].smc_count++;
191 tsp_stats[linear_id].eret_count++;
192 tsp_stats[linear_id].cpu_off_count++;
193
Dan Handley91b624e2014-07-29 17:14:00 +0100194#if LOG_LEVEL >= LOG_LEVEL_INFO
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000195 spin_lock(&console_lock);
Sandrine Bailleux8723adf2015-02-05 15:42:31 +0000196 INFO("TSP: cpu 0x%lx off request\n", mpidr);
197 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n", mpidr,
Dan Handley91b624e2014-07-29 17:14:00 +0100198 tsp_stats[linear_id].smc_count,
199 tsp_stats[linear_id].eret_count,
200 tsp_stats[linear_id].cpu_off_count);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000201 spin_unlock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +0100202#endif
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000203
Achin Gupta607084e2014-02-09 18:24:19 +0000204 /* Indicate to the SPD that we have completed this request */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000205 return set_smc_args(TSP_OFF_DONE, 0, 0, 0, 0, 0, 0, 0);
206}
207
208/*******************************************************************************
209 * This function performs any book keeping in the test secure payload before
210 * this cpu's architectural state is saved in response to an earlier psci
211 * cpu_suspend request.
212 ******************************************************************************/
Soby Mathewf5121572014-09-30 11:19:51 +0100213tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000214 uint64_t arg1,
215 uint64_t arg2,
216 uint64_t arg3,
217 uint64_t arg4,
218 uint64_t arg5,
219 uint64_t arg6,
220 uint64_t arg7)
221{
222 uint64_t mpidr = read_mpidr();
223 uint32_t linear_id = platform_get_core_pos(mpidr);
224
Achin Guptabbc33f22014-05-09 13:33:42 +0100225 /*
226 * Save the time context and disable it to prevent the secure timer
227 * interrupt from interfering with wakeup from the suspend state.
228 */
229 tsp_generic_timer_save();
230 tsp_generic_timer_stop();
231
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000232 /* Update this cpu's statistics */
233 tsp_stats[linear_id].smc_count++;
234 tsp_stats[linear_id].eret_count++;
235 tsp_stats[linear_id].cpu_suspend_count++;
236
Dan Handley91b624e2014-07-29 17:14:00 +0100237#if LOG_LEVEL >= LOG_LEVEL_INFO
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000238 spin_lock(&console_lock);
Sandrine Bailleux8723adf2015-02-05 15:42:31 +0000239 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
Dan Handley91b624e2014-07-29 17:14:00 +0100240 mpidr,
241 tsp_stats[linear_id].smc_count,
242 tsp_stats[linear_id].eret_count,
243 tsp_stats[linear_id].cpu_suspend_count);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000244 spin_unlock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +0100245#endif
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000246
Achin Gupta607084e2014-02-09 18:24:19 +0000247 /* Indicate to the SPD that we have completed this request */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000248 return set_smc_args(TSP_SUSPEND_DONE, 0, 0, 0, 0, 0, 0, 0);
249}
250
251/*******************************************************************************
252 * This function performs any book keeping in the test secure payload after this
253 * cpu's architectural state has been restored after wakeup from an earlier psci
254 * cpu_suspend request.
255 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100256tsp_args_t *tsp_cpu_resume_main(uint64_t suspend_level,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000257 uint64_t arg1,
258 uint64_t arg2,
259 uint64_t arg3,
260 uint64_t arg4,
261 uint64_t arg5,
262 uint64_t arg6,
263 uint64_t arg7)
264{
265 uint64_t mpidr = read_mpidr();
266 uint32_t linear_id = platform_get_core_pos(mpidr);
267
Achin Guptabbc33f22014-05-09 13:33:42 +0100268 /* Restore the generic timer context */
269 tsp_generic_timer_restore();
270
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000271 /* Update this cpu's statistics */
272 tsp_stats[linear_id].smc_count++;
273 tsp_stats[linear_id].eret_count++;
274 tsp_stats[linear_id].cpu_resume_count++;
275
Dan Handley91b624e2014-07-29 17:14:00 +0100276#if LOG_LEVEL >= LOG_LEVEL_INFO
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000277 spin_lock(&console_lock);
Sandrine Bailleux8723adf2015-02-05 15:42:31 +0000278 INFO("TSP: cpu 0x%lx resumed. suspend level %ld\n",
Dan Handley91b624e2014-07-29 17:14:00 +0100279 mpidr, suspend_level);
Sandrine Bailleux8723adf2015-02-05 15:42:31 +0000280 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
Dan Handley91b624e2014-07-29 17:14:00 +0100281 mpidr,
282 tsp_stats[linear_id].smc_count,
283 tsp_stats[linear_id].eret_count,
284 tsp_stats[linear_id].cpu_suspend_count);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000285 spin_unlock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +0100286#endif
Achin Gupta607084e2014-02-09 18:24:19 +0000287 /* Indicate to the SPD that we have completed this request */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000288 return set_smc_args(TSP_RESUME_DONE, 0, 0, 0, 0, 0, 0, 0);
289}
290
291/*******************************************************************************
Juan Castillo4dc4a472014-08-12 11:17:06 +0100292 * This function performs any remaining bookkeeping in the test secure payload
293 * before the system is switched off (in response to a psci SYSTEM_OFF request)
294 ******************************************************************************/
295tsp_args_t *tsp_system_off_main(uint64_t arg0,
296 uint64_t arg1,
297 uint64_t arg2,
298 uint64_t arg3,
299 uint64_t arg4,
300 uint64_t arg5,
301 uint64_t arg6,
302 uint64_t arg7)
303{
304 uint64_t mpidr = read_mpidr();
305 uint32_t linear_id = platform_get_core_pos(mpidr);
306
307 /* Update this cpu's statistics */
308 tsp_stats[linear_id].smc_count++;
309 tsp_stats[linear_id].eret_count++;
310
311#if LOG_LEVEL >= LOG_LEVEL_INFO
312 spin_lock(&console_lock);
Sandrine Bailleux8723adf2015-02-05 15:42:31 +0000313 INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", mpidr);
314 INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", mpidr,
Juan Castillo4dc4a472014-08-12 11:17:06 +0100315 tsp_stats[linear_id].smc_count,
316 tsp_stats[linear_id].eret_count);
317 spin_unlock(&console_lock);
318#endif
319
320 /* Indicate to the SPD that we have completed this request */
321 return set_smc_args(TSP_SYSTEM_OFF_DONE, 0, 0, 0, 0, 0, 0, 0);
322}
323
324/*******************************************************************************
325 * This function performs any remaining bookkeeping in the test secure payload
326 * before the system is reset (in response to a psci SYSTEM_RESET request)
327 ******************************************************************************/
328tsp_args_t *tsp_system_reset_main(uint64_t arg0,
329 uint64_t arg1,
330 uint64_t arg2,
331 uint64_t arg3,
332 uint64_t arg4,
333 uint64_t arg5,
334 uint64_t arg6,
335 uint64_t arg7)
336{
337 uint64_t mpidr = read_mpidr();
338 uint32_t linear_id = platform_get_core_pos(mpidr);
339
340 /* Update this cpu's statistics */
341 tsp_stats[linear_id].smc_count++;
342 tsp_stats[linear_id].eret_count++;
343
344#if LOG_LEVEL >= LOG_LEVEL_INFO
345 spin_lock(&console_lock);
Sandrine Bailleux8723adf2015-02-05 15:42:31 +0000346 INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", mpidr);
347 INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", mpidr,
Juan Castillo4dc4a472014-08-12 11:17:06 +0100348 tsp_stats[linear_id].smc_count,
349 tsp_stats[linear_id].eret_count);
350 spin_unlock(&console_lock);
351#endif
352
353 /* Indicate to the SPD that we have completed this request */
354 return set_smc_args(TSP_SYSTEM_RESET_DONE, 0, 0, 0, 0, 0, 0, 0);
355}
356
357/*******************************************************************************
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000358 * TSP fast smc handler. The secure monitor jumps to this function by
359 * doing the ERET after populating X0-X7 registers. The arguments are received
360 * in the function arguments in order. Once the service is rendered, this
Soby Mathew9f71f702014-05-09 20:49:17 +0100361 * function returns to Secure Monitor by raising SMC.
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000362 ******************************************************************************/
Soby Mathew9f71f702014-05-09 20:49:17 +0100363tsp_args_t *tsp_smc_handler(uint64_t func,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000364 uint64_t arg1,
365 uint64_t arg2,
366 uint64_t arg3,
367 uint64_t arg4,
368 uint64_t arg5,
369 uint64_t arg6,
370 uint64_t arg7)
371{
Achin Gupta916a2c12014-02-09 23:11:46 +0000372 uint64_t results[2];
373 uint64_t service_args[2];
374 uint64_t mpidr = read_mpidr();
375 uint32_t linear_id = platform_get_core_pos(mpidr);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000376
Achin Gupta916a2c12014-02-09 23:11:46 +0000377 /* Update this cpu's statistics */
378 tsp_stats[linear_id].smc_count++;
379 tsp_stats[linear_id].eret_count++;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000380
Sandrine Bailleux8723adf2015-02-05 15:42:31 +0000381 INFO("TSP: cpu 0x%lx received %s smc 0x%lx\n", mpidr,
Dan Handley91b624e2014-07-29 17:14:00 +0100382 ((func >> 31) & 1) == 1 ? "fast" : "standard",
383 func);
Sandrine Bailleux8723adf2015-02-05 15:42:31 +0000384 INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", mpidr,
Dan Handley91b624e2014-07-29 17:14:00 +0100385 tsp_stats[linear_id].smc_count,
386 tsp_stats[linear_id].eret_count);
Achin Gupta916a2c12014-02-09 23:11:46 +0000387
388 /* Render secure services and obtain results here */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000389 results[0] = arg1;
390 results[1] = arg2;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000391
392 /*
393 * Request a service back from dispatcher/secure monitor. This call
394 * return and thereafter resume exectuion
395 */
396 tsp_get_magic(service_args);
397
398 /* Determine the function to perform based on the function ID */
Soby Mathew9f71f702014-05-09 20:49:17 +0100399 switch (TSP_BARE_FID(func)) {
400 case TSP_ADD:
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000401 results[0] += service_args[0];
402 results[1] += service_args[1];
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000403 break;
Soby Mathew9f71f702014-05-09 20:49:17 +0100404 case TSP_SUB:
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000405 results[0] -= service_args[0];
406 results[1] -= service_args[1];
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000407 break;
Soby Mathew9f71f702014-05-09 20:49:17 +0100408 case TSP_MUL:
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000409 results[0] *= service_args[0];
410 results[1] *= service_args[1];
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000411 break;
Soby Mathew9f71f702014-05-09 20:49:17 +0100412 case TSP_DIV:
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000413 results[0] /= service_args[0] ? service_args[0] : 1;
414 results[1] /= service_args[1] ? service_args[1] : 1;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000415 break;
416 default:
417 break;
418 }
419
Soby Mathew9f71f702014-05-09 20:49:17 +0100420 return set_smc_args(func, 0,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000421 results[0],
422 results[1],
Soby Mathew9f71f702014-05-09 20:49:17 +0100423 0, 0, 0, 0);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000424}
425