| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013, ARM Limited. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | .globl read_icc_sre_el1 |
| 32 | .globl read_icc_sre_el2 |
| 33 | .globl read_icc_sre_el3 |
| 34 | .globl write_icc_sre_el1 |
| 35 | .globl write_icc_sre_el2 |
| 36 | .globl write_icc_sre_el3 |
| 37 | .globl write_icc_pmr_el1 |
| 38 | |
| 39 | |
| 40 | /* |
| 41 | * Register definitions used by GCC for GICv3 access. |
| 42 | * These are defined by ARMCC, so keep them in the GCC specific code for now. |
| 43 | */ |
| 44 | #define ICC_SRE_EL1 S3_0_C12_C12_5 |
| 45 | #define ICC_SRE_EL2 S3_4_C12_C9_5 |
| 46 | #define ICC_SRE_EL3 S3_6_C12_C12_5 |
| 47 | #define ICC_CTLR_EL1 S3_0_C12_C12_4 |
| 48 | #define ICC_CTLR_EL3 S3_6_C12_C12_4 |
| 49 | #define ICC_PMR_EL1 S3_0_C4_C6_0 |
| 50 | |
| Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame^] | 51 | .section .text, "ax"; .align 3 |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 52 | |
| 53 | read_icc_sre_el1:; .type read_icc_sre_el1, %function |
| 54 | mrs x0, ICC_SRE_EL1 |
| 55 | ret |
| 56 | |
| 57 | |
| 58 | read_icc_sre_el2:; .type read_icc_sre_el2, %function |
| 59 | mrs x0, ICC_SRE_EL2 |
| 60 | ret |
| 61 | |
| 62 | |
| 63 | read_icc_sre_el3:; .type read_icc_sre_el3, %function |
| 64 | mrs x0, ICC_SRE_EL3 |
| 65 | ret |
| 66 | |
| 67 | |
| 68 | write_icc_sre_el1:; .type write_icc_sre_el1, %function |
| 69 | msr ICC_SRE_EL1, x0 |
| 70 | isb |
| 71 | ret |
| 72 | |
| 73 | |
| 74 | write_icc_sre_el2:; .type write_icc_sre_el2, %function |
| 75 | msr ICC_SRE_EL2, x0 |
| 76 | isb |
| 77 | ret |
| 78 | |
| 79 | |
| 80 | write_icc_sre_el3:; .type write_icc_sre_el3, %function |
| 81 | msr ICC_SRE_EL3, x0 |
| 82 | isb |
| 83 | ret |
| 84 | |
| 85 | |
| 86 | write_icc_pmr_el1:; .type write_icc_pmr_el1, %function |
| 87 | msr ICC_PMR_EL1, x0 |
| 88 | isb |
| 89 | ret |