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Juan Pablo Conde49f70662023-07-06 15:38:59 -05001/*
2 * Copyright (c) 2023, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef NEVIS_H
8#define NEVIS_H
9
10#define NEVIS_MIDR U(0x410FD8A0)
11
12/*******************************************************************************
13 * CPU Extended Control register specific definitions
14 ******************************************************************************/
15#define NEVIS_CPUECTLR_EL1 S3_0_C15_C1_4
16
17/*******************************************************************************
18 * CPU Power Control register specific definitions
19 ******************************************************************************/
20#define NEVIS_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7
21#define NEVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
22
23#endif /* NEVIS_H */