blob: 6e784f6f5357e2be290cec1c78e32df4f5ab18f5 [file] [log] [blame]
Joel Huttona7c46872018-01-10 16:06:07 +00001/*
Govindraj Rajaeee28e72023-08-01 15:52:40 -05002 * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
Joel Huttona7c46872018-01-10 16:06:07 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
John Tsichritzis16e6d9f2019-02-19 14:01:55 +00007#ifndef NEOVERSE_E1_H
8#define NEOVERSE_E1_H
Joel Huttona7c46872018-01-10 16:06:07 +00009
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +000010#include <lib/utils_def.h>
11
John Tsichritzisa5447ec2019-03-15 15:40:27 +000012#define NEOVERSE_E1_MIDR U(0x410FD4A0)
Joel Huttona7c46872018-01-10 16:06:07 +000013
14/*******************************************************************************
15 * CPU Extended Control register specific definitions.
16 ******************************************************************************/
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000017#define NEOVERSE_E1_ECTLR_EL1 S3_0_C15_C1_4
Joel Huttona7c46872018-01-10 16:06:07 +000018
19/*******************************************************************************
20 * CPU Auxiliary Control register specific definitions.
21 ******************************************************************************/
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000022#define NEOVERSE_E1_CPUACTLR_EL1 S3_0_C15_C1_0
Joel Huttona7c46872018-01-10 16:06:07 +000023
24/*******************************************************************************
25 * CPU Power Control register specific definitions.
26 ******************************************************************************/
27
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000028#define NEOVERSE_E1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
29#define NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
Joel Huttona7c46872018-01-10 16:06:07 +000030
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000031#endif /* NEOVERSE_E1_H */