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git01.mediatek.com / filogic / atf / 8d22ec3ad8fcb1541a5852d5665a9c7433b2e592 / . / lib / cpus / aarch64 / cortex_a73.S
blob: 11680a09dd09ef016613e23daa43b9c98da2e255 [file] [log] [blame]
Yatharth Kochar63af6872016-02-09 12:00:03 +0000[diff] [blame]1/*
Dimitris Papastamos858bd612018-01-16 10:32:47 +0000[diff] [blame]2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Yatharth Kochar63af6872016-02-09 12:00:03 +0000[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Yatharth Kochar63af6872016-02-09 12:00:03 +0000[diff] [blame]5 */
6#include <arch.h>
7#include <asm_macros.S>
8#include <bl_common.h>
9#include <cortex_a73.h>
10#include <cpu_macros.S>
11#include <plat_macros.S>
12
13 /* ---------------------------------------------
14 * Disable L1 data cache
15 * ---------------------------------------------
16 */
17func cortex_a73_disable_dcache
18 mrs x1, sctlr_el3
19 bic x1, x1, #SCTLR_C_BIT
20 msr sctlr_el3, x1
21 isb
22 ret
23endfunc cortex_a73_disable_dcache
24
25 /* ---------------------------------------------
26 * Disable intra-cluster coherency
27 * ---------------------------------------------
28 */
29func cortex_a73_disable_smp
30 mrs x0, CORTEX_A73_CPUECTLR_EL1
31 bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
32 msr CORTEX_A73_CPUECTLR_EL1, x0
33 isb
34 dsb sy
35 ret
36endfunc cortex_a73_disable_smp
37
38func cortex_a73_reset_func
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000[diff] [blame]39#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
40 adr x0, workaround_bpiall_vbar0_runtime_exceptions
41 msr vbar_el3, x0
42#endif
43
Yatharth Kochar63af6872016-02-09 12:00:03 +0000[diff] [blame]44 /* ---------------------------------------------
45 * Enable the SMP bit.
46 * Clobbers : x0
47 * ---------------------------------------------
48 */
49 mrs x0, CORTEX_A73_CPUECTLR_EL1
50 orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
51 msr CORTEX_A73_CPUECTLR_EL1, x0
52 isb
53 ret
54endfunc cortex_a73_reset_func
55
56func cortex_a73_core_pwr_dwn
57 mov x18, x30
58
59 /* ---------------------------------------------
60 * Turn off caches.
61 * ---------------------------------------------
62 */
63 bl cortex_a73_disable_dcache
64
65 /* ---------------------------------------------
66 * Flush L1 caches.
67 * ---------------------------------------------
68 */
69 mov x0, #DCCISW
70 bl dcsw_op_level1
71
72 /* ---------------------------------------------
73 * Come out of intra cluster coherency
74 * ---------------------------------------------
75 */
76 mov x30, x18
77 b cortex_a73_disable_smp
78endfunc cortex_a73_core_pwr_dwn
79
80func cortex_a73_cluster_pwr_dwn
81 mov x18, x30
82
83 /* ---------------------------------------------
84 * Turn off caches.
85 * ---------------------------------------------
86 */
87 bl cortex_a73_disable_dcache
88
89 /* ---------------------------------------------
90 * Flush L1 caches.
91 * ---------------------------------------------
92 */
93 mov x0, #DCCISW
94 bl dcsw_op_level1
95
96 /* ---------------------------------------------
97 * Disable the optional ACP.
98 * ---------------------------------------------
99 */
100 bl plat_disable_acp
101
102 /* ---------------------------------------------
103 * Flush L2 caches.
104 * ---------------------------------------------
105 */
106 mov x0, #DCCISW
107 bl dcsw_op_level2
108
109 /* ---------------------------------------------
110 * Come out of intra cluster coherency
111 * ---------------------------------------------
112 */
113 mov x30, x18
114 b cortex_a73_disable_smp
115endfunc cortex_a73_cluster_pwr_dwn
116
Dimitris Papastamos858bd612018-01-16 10:32:47 +0000[diff] [blame]117func check_errata_cve_2017_5715
118#if WORKAROUND_CVE_2017_5715
119 mov x0, #ERRATA_APPLIES
120#else
121 mov x0, #ERRATA_MISSING
122#endif
123 ret
124endfunc check_errata_cve_2017_5715
125
126#if REPORT_ERRATA
127/*
128 * Errata printing function for Cortex A75. Must follow AAPCS.
129 */
130func cortex_a73_errata_report
131 stp x8, x30, [sp, #-16]!
132
133 bl cpu_get_rev_var
134 mov x8, x0
135
136 /*
137 * Report all errata. The revision-variant information is passed to
138 * checking functions of each errata.
139 */
140 report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715
141
142 ldp x8, x30, [sp], #16
143 ret
144endfunc cortex_a73_errata_report
145#endif
146
Yatharth Kochar63af6872016-02-09 12:00:03 +0000[diff] [blame]147 /* ---------------------------------------------
148 * This function provides cortex_a73 specific
149 * register information for crash reporting.
150 * It needs to return with x6 pointing to
151 * a list of register names in ascii and
152 * x8 - x15 having values of registers to be
153 * reported.
154 * ---------------------------------------------
155 */
156.section .rodata.cortex_a73_regs, "aS"
157cortex_a73_regs: /* The ascii list of register names to be reported */
Naga Sureshkumar Relli6a72a912016-07-01 12:52:41 +0530[diff] [blame]158 .asciz "cpuectlr_el1", "l2merrsr_el1", ""
Yatharth Kochar63af6872016-02-09 12:00:03 +0000[diff] [blame]159
160func cortex_a73_cpu_reg_dump
161 adr x6, cortex_a73_regs
162 mrs x8, CORTEX_A73_CPUECTLR_EL1
Naga Sureshkumar Relli6a72a912016-07-01 12:52:41 +0530[diff] [blame]163 mrs x9, CORTEX_A73_L2MERRSR_EL1
Yatharth Kochar63af6872016-02-09 12:00:03 +0000[diff] [blame]164 ret
165endfunc cortex_a73_cpu_reg_dump
166
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +0000[diff] [blame]167declare_cpu_ops cortex_a73, CORTEX_A73_MIDR, \
168 cortex_a73_reset_func, \
169 cortex_a73_core_pwr_dwn, \
170 cortex_a73_cluster_pwr_dwn