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Jiafei Pan46367ad2018-03-02 07:23:30 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +01008#include <assert.h>
Jiafei Pan46367ad2018-03-02 07:23:30 +00009#include <debug.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010010#include <delay_timer.h>
11#include <endian.h>
Jiafei Pan46367ad2018-03-02 07:23:30 +000012#include <errno.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010013#include <gicv2.h>
14#include <mmio.h>
Jiafei Pan46367ad2018-03-02 07:23:30 +000015#include <platform.h>
16#include <psci.h>
Jiafei Pan46367ad2018-03-02 07:23:30 +000017#include "platform_def.h"
18
19#define LS_SCFG_BASE 0x01570000
20/* register to store warm boot entry, big endian, higher 32bit */
21#define LS_SCFG_SCRATCHRW0_OFFSET 0x600
22/* register to store warm boot entry, big endian, lower 32bit */
23#define LS_SCFG_SCRATCHRW1_OFFSET 0x604
24#define LS_SCFG_COREBCR_OFFSET 0x680
25
26#define LS_DCFG_BASE 0x01EE0000
27#define LS_DCFG_RSTCR_OFFSET 0x0B0
28#define LS_DCFG_RSTRQMR1_OFFSET 0x0C0
29#define LS_DCFG_BRR_OFFSET 0x0E4
30
31#define LS_SCFG_CORE0_SFT_RST_OFFSET 0x130
32#define LS_SCFG_CORE1_SFT_RST_OFFSET 0x134
33#define LS_SCFG_CORE2_SFT_RST_OFFSET 0x138
34#define LS_SCFG_CORE3_SFT_RST_OFFSET 0x13C
35
36#define LS_SCFG_CORESRENCR_OFFSET 0x204
37
38#define LS_SCFG_RVBAR0_0_OFFSET 0x220
39#define LS_SCFG_RVBAR0_1_OFFSET 0x224
40
41#define LS_SCFG_RVBAR1_0_OFFSET 0x228
42#define LS_SCFG_RVBAR1_1_OFFSET 0x22C
43
44#define LS_SCFG_RVBAR2_0_OFFSET 0x230
45#define LS_SCFG_RVBAR2_1_OFFSET 0x234
46
47#define LS_SCFG_RVBAR3_0_OFFSET 0x238
48#define LS_SCFG_RVBAR3_1_OFFSET 0x23C
49
50/* the entry for core warm boot */
51static uintptr_t warmboot_entry;
52
53/* warm reset single core */
54static void ls1043_reset_core(int core_pos)
55{
56 assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT);
57
58 /* set 0 in RVBAR, boot from bootrom at 0x0 */
59 mmio_write_32(LS_SCFG_BASE + LS_SCFG_RVBAR0_0_OFFSET + core_pos * 8,
60 0);
61 mmio_write_32(LS_SCFG_BASE + LS_SCFG_RVBAR0_1_OFFSET + core_pos * 8,
62 0);
63
64 dsb();
65 /* enable core soft reset */
66 mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORESRENCR_OFFSET,
67 htobe32(1 << 31));
68 dsb();
69 isb();
70 /* reset core */
71 mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORE0_SFT_RST_OFFSET +
72 core_pos * 4, htobe32(1 << 31));
73 mdelay(10);
74}
75
76static void __dead2 ls1043_system_reset(void)
77{
78 /* clear reset request mask bits */
79 mmio_write_32(LS_DCFG_BASE + LS_DCFG_RSTRQMR1_OFFSET, 0);
80
81 /* set reset request bit */
82 mmio_write_32(LS_DCFG_BASE + LS_DCFG_RSTCR_OFFSET,
83 htobe32((uint32_t)0x2));
84
85 /* system will reset; if fail, enter wfi */
86 dsb();
87 isb();
88 wfi();
89
90 panic();
91}
92
93
94static int ls1043_pwr_domain_on(u_register_t mpidr)
95{
96 int core_pos = plat_core_pos_by_mpidr(mpidr);
Jiafei Pan62f44c02018-04-11 12:12:24 +000097 uint32_t core_mask, brr;
Jiafei Pan46367ad2018-03-02 07:23:30 +000098
99 assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT);
Jiafei Pan62f44c02018-04-11 12:12:24 +0000100 core_mask = 1 << core_pos;
Jiafei Pan46367ad2018-03-02 07:23:30 +0000101
102 /* set warm boot entry */
103 mmio_write_32(LS_SCFG_BASE + LS_SCFG_SCRATCHRW0_OFFSET,
104 htobe32((uint32_t)(warmboot_entry >> 32)));
105
106 mmio_write_32(LS_SCFG_BASE + LS_SCFG_SCRATCHRW1_OFFSET,
107 htobe32((uint32_t)warmboot_entry));
108
109 dsb();
110
111 brr = be32toh(mmio_read_32(LS_DCFG_BASE + LS_DCFG_BRR_OFFSET));
112 if (brr & core_mask) {
113 /* core has been released, must reset it to restart */
114 ls1043_reset_core(core_pos);
115
116 /* set bit in core boot control register to enable boot */
117 mmio_write_32(LS_SCFG_BASE + LS_SCFG_COREBCR_OFFSET,
118 htobe32(core_mask));
119
120 } else {
121 /* set bit in core boot control register to enable boot */
122 mmio_write_32(LS_SCFG_BASE + LS_SCFG_COREBCR_OFFSET,
123 htobe32(core_mask));
124
125 /* release core */
126 mmio_write_32(LS_DCFG_BASE + LS_DCFG_BRR_OFFSET,
127 htobe32(brr | core_mask));
128 }
129
130 mdelay(20);
131
132 /* wake core in case it is in wfe */
133 dsb();
134 isb();
135 sev();
136
137 return PSCI_E_SUCCESS;
138}
139
140static void ls1043_pwr_domain_on_finish(const psci_power_state_t *target_state)
141{
142 /* Per cpu gic distributor setup */
143 gicv2_pcpu_distif_init();
144
145 /* Enable the gic CPU interface */
146 gicv2_cpuif_enable();
147}
148
149static void ls1043_pwr_domain_off(const psci_power_state_t *target_state)
150{
151 /* Disable the gic CPU interface */
152 gicv2_cpuif_disable();
153}
154
155static plat_psci_ops_t ls1043_psci_pm_ops = {
156 .system_reset = ls1043_system_reset,
157 .pwr_domain_on = ls1043_pwr_domain_on,
158 .pwr_domain_on_finish = ls1043_pwr_domain_on_finish,
159 .pwr_domain_off = ls1043_pwr_domain_off,
160};
161
162int plat_setup_psci_ops(uintptr_t sec_entrypoint,
163 const plat_psci_ops_t **psci_ops)
164{
165 warmboot_entry = sec_entrypoint;
166 *psci_ops = &ls1043_psci_pm_ops;
167 return 0;
168}