| Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <bl_common.h> |
| 10 | #include <cortex_a35.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | |
| 14 | /* --------------------------------------------- |
| 15 | * Disable L1 data cache and unified L2 cache |
| 16 | * --------------------------------------------- |
| 17 | */ |
| 18 | func cortex_a35_disable_dcache |
| 19 | mrs x1, sctlr_el3 |
| 20 | bic x1, x1, #SCTLR_C_BIT |
| 21 | msr sctlr_el3, x1 |
| 22 | isb |
| 23 | ret |
| 24 | endfunc cortex_a35_disable_dcache |
| 25 | |
| 26 | /* --------------------------------------------- |
| 27 | * Disable intra-cluster coherency |
| 28 | * --------------------------------------------- |
| 29 | */ |
| 30 | func cortex_a35_disable_smp |
| 31 | mrs x0, CORTEX_A35_CPUECTLR_EL1 |
| 32 | bic x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT |
| 33 | msr CORTEX_A35_CPUECTLR_EL1, x0 |
| 34 | isb |
| 35 | dsb sy |
| 36 | ret |
| 37 | endfunc cortex_a35_disable_smp |
| 38 | |
| 39 | /* ------------------------------------------------- |
| 40 | * The CPU Ops reset function for Cortex-A35. |
| 41 | * Clobbers: x0 |
| 42 | * ------------------------------------------------- |
| 43 | */ |
| 44 | func cortex_a35_reset_func |
| 45 | /* --------------------------------------------- |
| Sandrine Bailleux | f12a31d | 2016-01-29 14:37:58 +0000 | [diff] [blame] | 46 | * Enable the SMP bit. |
| Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 47 | * --------------------------------------------- |
| 48 | */ |
| 49 | mrs x0, CORTEX_A35_CPUECTLR_EL1 |
| Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 50 | orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT |
| 51 | msr CORTEX_A35_CPUECTLR_EL1, x0 |
| Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 52 | isb |
| 53 | ret |
| 54 | endfunc cortex_a35_reset_func |
| 55 | |
| 56 | func cortex_a35_core_pwr_dwn |
| 57 | mov x18, x30 |
| 58 | |
| 59 | /* --------------------------------------------- |
| 60 | * Turn off caches. |
| 61 | * --------------------------------------------- |
| 62 | */ |
| 63 | bl cortex_a35_disable_dcache |
| 64 | |
| 65 | /* --------------------------------------------- |
| 66 | * Flush L1 caches. |
| 67 | * --------------------------------------------- |
| 68 | */ |
| 69 | mov x0, #DCCISW |
| 70 | bl dcsw_op_level1 |
| 71 | |
| 72 | /* --------------------------------------------- |
| 73 | * Come out of intra cluster coherency |
| 74 | * --------------------------------------------- |
| 75 | */ |
| 76 | mov x30, x18 |
| 77 | b cortex_a35_disable_smp |
| 78 | endfunc cortex_a35_core_pwr_dwn |
| 79 | |
| 80 | func cortex_a35_cluster_pwr_dwn |
| 81 | mov x18, x30 |
| 82 | |
| 83 | /* --------------------------------------------- |
| 84 | * Turn off caches. |
| 85 | * --------------------------------------------- |
| 86 | */ |
| 87 | bl cortex_a35_disable_dcache |
| 88 | |
| 89 | /* --------------------------------------------- |
| 90 | * Flush L1 caches. |
| 91 | * --------------------------------------------- |
| 92 | */ |
| 93 | mov x0, #DCCISW |
| 94 | bl dcsw_op_level1 |
| 95 | |
| 96 | /* --------------------------------------------- |
| 97 | * Disable the optional ACP. |
| 98 | * --------------------------------------------- |
| 99 | */ |
| 100 | bl plat_disable_acp |
| 101 | |
| 102 | /* --------------------------------------------- |
| 103 | * Flush L2 caches. |
| 104 | * --------------------------------------------- |
| 105 | */ |
| 106 | mov x0, #DCCISW |
| 107 | bl dcsw_op_level2 |
| 108 | |
| 109 | /* --------------------------------------------- |
| 110 | * Come out of intra cluster coherency |
| 111 | * --------------------------------------------- |
| 112 | */ |
| 113 | mov x30, x18 |
| 114 | b cortex_a35_disable_smp |
| 115 | endfunc cortex_a35_cluster_pwr_dwn |
| 116 | |
| Soby Mathew | 0980dce | 2018-09-17 04:34:35 +0100 | [diff] [blame] | 117 | #if REPORT_ERRATA |
| 118 | /* |
| 119 | * Errata printing function for Cortex A35. Must follow AAPCS. |
| 120 | */ |
| 121 | func cortex_a35_errata_report |
| 122 | ret |
| 123 | endfunc cortex_a35_errata_report |
| 124 | #endif |
| 125 | |
| 126 | |
| Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 127 | /* --------------------------------------------- |
| 128 | * This function provides cortex_a35 specific |
| 129 | * register information for crash reporting. |
| 130 | * It needs to return with x6 pointing to |
| 131 | * a list of register names in ascii and |
| 132 | * x8 - x15 having values of registers to be |
| 133 | * reported. |
| 134 | * --------------------------------------------- |
| 135 | */ |
| 136 | .section .rodata.cortex_a35_regs, "aS" |
| 137 | cortex_a35_regs: /* The ascii list of register names to be reported */ |
| 138 | .asciz "cpuectlr_el1", "" |
| 139 | |
| 140 | func cortex_a35_cpu_reg_dump |
| 141 | adr x6, cortex_a35_regs |
| 142 | mrs x8, CORTEX_A35_CPUECTLR_EL1 |
| 143 | ret |
| 144 | endfunc cortex_a35_cpu_reg_dump |
| 145 | |
| Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 146 | declare_cpu_ops cortex_a35, CORTEX_A35_MIDR, \ |
| 147 | cortex_a35_reset_func, \ |
| 148 | cortex_a35_core_pwr_dwn, \ |
| 149 | cortex_a35_cluster_pwr_dwn |