Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Soby Mathew | 7c6df5b | 2018-01-15 14:43:42 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 6 | #ifndef ARM_DEF_H |
| 7 | #define ARM_DEF_H |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 8 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 9 | #include <arch.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 10 | #include <common_def.h> |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 11 | #include <gic_common.h> |
| 12 | #include <interrupt_props.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 13 | #include <platform_def.h> |
Juan Castillo | 9b265a8 | 2015-05-07 14:52:44 +0100 | [diff] [blame] | 14 | #include <tbbr_img_def.h> |
Scott Branden | bf404c0 | 2017-04-10 11:45:52 -0700 | [diff] [blame] | 15 | #include <utils_def.h> |
Antonio Nino Diaz | 719bf85 | 2017-02-23 17:22:58 +0000 | [diff] [blame] | 16 | #include <xlat_tables_defs.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 17 | |
| 18 | |
| 19 | /****************************************************************************** |
| 20 | * Definitions common to all ARM standard platforms |
| 21 | *****************************************************************************/ |
| 22 | |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 23 | /* Special value used to verify platform parameters from BL2 to BL31 */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 24 | #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 25 | |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 26 | #define ARM_SYSTEM_COUNT 1 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 27 | |
| 28 | #define ARM_CACHE_WRITEBACK_SHIFT 6 |
| 29 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 30 | /* |
| 31 | * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The |
| 32 | * power levels have a 1:1 mapping with the MPIDR affinity levels. |
| 33 | */ |
| 34 | #define ARM_PWR_LVL0 MPIDR_AFFLVL0 |
| 35 | #define ARM_PWR_LVL1 MPIDR_AFFLVL1 |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 36 | #define ARM_PWR_LVL2 MPIDR_AFFLVL2 |
Chandni Cherukuri | 9ec4a11 | 2018-10-16 14:42:19 +0530 | [diff] [blame] | 37 | #define ARM_PWR_LVL3 MPIDR_AFFLVL3 |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 38 | |
| 39 | /* |
| 40 | * Macros for local power states in ARM platforms encoded by State-ID field |
| 41 | * within the power-state parameter. |
| 42 | */ |
| 43 | /* Local power state for power domains in Run state. */ |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 44 | #define ARM_LOCAL_STATE_RUN U(0) |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 45 | /* Local power state for retention. Valid only for CPU power domains */ |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 46 | #define ARM_LOCAL_STATE_RET U(1) |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 47 | /* Local power state for OFF/power-down. Valid for CPU and cluster power |
| 48 | domains */ |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 49 | #define ARM_LOCAL_STATE_OFF U(2) |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 50 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 51 | /* Memory location options for TSP */ |
| 52 | #define ARM_TRUSTED_SRAM_ID 0 |
| 53 | #define ARM_TRUSTED_DRAM_ID 1 |
| 54 | #define ARM_DRAM_ID 2 |
| 55 | |
| 56 | /* The first 4KB of Trusted SRAM are used as shared memory */ |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 57 | #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 58 | #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 59 | #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 60 | |
| 61 | /* The remaining Trusted SRAM is used to load the BL images */ |
| 62 | #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ |
| 63 | ARM_SHARED_RAM_SIZE) |
| 64 | #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ |
| 65 | ARM_SHARED_RAM_SIZE) |
| 66 | |
| 67 | /* |
| 68 | * The top 16MB of DRAM1 is configured as secure access only using the TZC |
| 69 | * - SCP TZC DRAM: If present, DRAM reserved for SCP use |
| 70 | * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use |
| 71 | */ |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 72 | #define ARM_TZC_DRAM1_SIZE UL(0x01000000) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 73 | |
| 74 | #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ |
| 75 | ARM_DRAM1_SIZE - \ |
| 76 | ARM_SCP_TZC_DRAM1_SIZE) |
| 77 | #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE |
| 78 | #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ |
| 79 | ARM_SCP_TZC_DRAM1_SIZE - 1) |
| 80 | |
Soby Mathew | 3b5156e | 2017-10-05 12:27:33 +0100 | [diff] [blame] | 81 | /* |
| 82 | * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime |
| 83 | * firmware. This region is meant to be NOLOAD and will not be zero |
| 84 | * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be |
| 85 | * placed here. |
| 86 | */ |
| 87 | #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE) |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 88 | #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */ |
Soby Mathew | 3b5156e | 2017-10-05 12:27:33 +0100 | [diff] [blame] | 89 | #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ |
| 90 | ARM_EL3_TZC_DRAM1_SIZE - 1) |
| 91 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 92 | #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ |
| 93 | ARM_DRAM1_SIZE - \ |
| 94 | ARM_TZC_DRAM1_SIZE) |
| 95 | #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ |
Soby Mathew | 3b5156e | 2017-10-05 12:27:33 +0100 | [diff] [blame] | 96 | (ARM_SCP_TZC_DRAM1_SIZE + \ |
| 97 | ARM_EL3_TZC_DRAM1_SIZE)) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 98 | #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ |
| 99 | ARM_AP_TZC_DRAM1_SIZE - 1) |
| 100 | |
Soby Mathew | 7e4d665 | 2017-05-10 11:50:30 +0100 | [diff] [blame] | 101 | /* Define the Access permissions for Secure peripherals to NS_DRAM */ |
| 102 | #if ARM_CRYPTOCELL_INTEG |
| 103 | /* |
| 104 | * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. |
| 105 | * This is required by CryptoCell to authenticate BL33 which is loaded |
| 106 | * into the Non Secure DDR. |
| 107 | */ |
| 108 | #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD |
| 109 | #else |
| 110 | #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE |
| 111 | #endif |
| 112 | |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 113 | #ifdef SPD_opteed |
| 114 | /* |
Jens Wiklander | ae73b16 | 2017-08-24 15:39:09 +0200 | [diff] [blame] | 115 | * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to |
| 116 | * load/authenticate the trusted os extra image. The first 512KB of |
| 117 | * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading |
| 118 | * for OPTEE is paged image which only include the paging part using |
| 119 | * virtual memory but without "init" data. OPTEE will copy the "init" data |
| 120 | * (from pager image) to the first 512KB of TZC_DRAM, and then copy the |
| 121 | * extra image behind the "init" data. |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 122 | */ |
Jens Wiklander | ae73b16 | 2017-08-24 15:39:09 +0200 | [diff] [blame] | 123 | #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ |
| 124 | ARM_AP_TZC_DRAM1_SIZE - \ |
| 125 | ARM_OPTEE_PAGEABLE_LOAD_SIZE) |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 126 | #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 127 | #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ |
| 128 | ARM_OPTEE_PAGEABLE_LOAD_BASE, \ |
| 129 | ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ |
| 130 | MT_MEMORY | MT_RW | MT_SECURE) |
Soby Mathew | 874fc9e | 2017-09-01 13:43:50 +0100 | [diff] [blame] | 131 | |
| 132 | /* |
| 133 | * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging |
| 134 | * support is enabled). |
| 135 | */ |
| 136 | #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ |
| 137 | BL32_BASE, \ |
| 138 | BL32_LIMIT - BL32_BASE, \ |
| 139 | MT_MEMORY | MT_RW | MT_SECURE) |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 140 | #endif /* SPD_opteed */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 141 | |
| 142 | #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE |
| 143 | #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ |
| 144 | ARM_TZC_DRAM1_SIZE) |
| 145 | #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ |
| 146 | ARM_NS_DRAM1_SIZE - 1) |
| 147 | |
Sandrine Bailleux | 6c32fc7 | 2018-10-31 14:28:17 +0100 | [diff] [blame] | 148 | #define ARM_DRAM1_BASE ULL(0x80000000) |
| 149 | #define ARM_DRAM1_SIZE ULL(0x80000000) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 150 | #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ |
| 151 | ARM_DRAM1_SIZE - 1) |
| 152 | |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 153 | #define ARM_DRAM2_BASE UL(0x880000000) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 154 | #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE |
| 155 | #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ |
| 156 | ARM_DRAM2_SIZE - 1) |
| 157 | |
| 158 | #define ARM_IRQ_SEC_PHY_TIMER 29 |
| 159 | |
| 160 | #define ARM_IRQ_SEC_SGI_0 8 |
| 161 | #define ARM_IRQ_SEC_SGI_1 9 |
| 162 | #define ARM_IRQ_SEC_SGI_2 10 |
| 163 | #define ARM_IRQ_SEC_SGI_3 11 |
| 164 | #define ARM_IRQ_SEC_SGI_4 12 |
| 165 | #define ARM_IRQ_SEC_SGI_5 13 |
| 166 | #define ARM_IRQ_SEC_SGI_6 14 |
| 167 | #define ARM_IRQ_SEC_SGI_7 15 |
| 168 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 169 | /* |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 170 | * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 |
| 171 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 172 | * as Group 0 interrupts. |
| 173 | */ |
| 174 | #define ARM_G1S_IRQ_PROPS(grp) \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 175 | INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 176 | GIC_INTR_CFG_LEVEL), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 177 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 178 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 179 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 180 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 181 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 182 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 183 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 184 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 185 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 186 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 187 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 188 | GIC_INTR_CFG_EDGE) |
| 189 | |
| 190 | #define ARM_G0_IRQ_PROPS(grp) \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 191 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 192 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 193 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 194 | GIC_INTR_CFG_EDGE) |
| 195 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 196 | #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ |
| 197 | ARM_SHARED_RAM_BASE, \ |
| 198 | ARM_SHARED_RAM_SIZE, \ |
Juan Castillo | 2e86cb1 | 2016-01-13 15:01:09 +0000 | [diff] [blame] | 199 | MT_DEVICE | MT_RW | MT_SECURE) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 200 | |
| 201 | #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ |
| 202 | ARM_NS_DRAM1_BASE, \ |
| 203 | ARM_NS_DRAM1_SIZE, \ |
| 204 | MT_MEMORY | MT_RW | MT_NS) |
| 205 | |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 206 | #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ |
| 207 | ARM_DRAM2_BASE, \ |
| 208 | ARM_DRAM2_SIZE, \ |
| 209 | MT_MEMORY | MT_RW | MT_NS) |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 210 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 211 | #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ |
| 212 | TSP_SEC_MEM_BASE, \ |
| 213 | TSP_SEC_MEM_SIZE, \ |
| 214 | MT_MEMORY | MT_RW | MT_SECURE) |
| 215 | |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 216 | #if ARM_BL31_IN_DRAM |
| 217 | #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ |
| 218 | BL31_BASE, \ |
| 219 | PLAT_ARM_MAX_BL31_SIZE, \ |
| 220 | MT_MEMORY | MT_RW | MT_SECURE) |
| 221 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 222 | |
Soby Mathew | 3b5156e | 2017-10-05 12:27:33 +0100 | [diff] [blame] | 223 | #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ |
| 224 | ARM_EL3_TZC_DRAM1_BASE, \ |
| 225 | ARM_EL3_TZC_DRAM1_SIZE, \ |
| 226 | MT_MEMORY | MT_RW | MT_SECURE) |
| 227 | |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 228 | /* |
John Tsichritzis | c34341a | 2018-07-30 13:41:52 +0100 | [diff] [blame] | 229 | * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to |
| 230 | * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides |
| 231 | * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order |
| 232 | * to be able to access the heap. |
| 233 | */ |
| 234 | #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ |
| 235 | BL1_RW_BASE, \ |
| 236 | BL1_RW_LIMIT - BL1_RW_BASE, \ |
| 237 | MT_MEMORY | MT_RW | MT_SECURE) |
| 238 | |
| 239 | /* |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 240 | * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section |
| 241 | * otherwise one region is defined containing both. |
| 242 | */ |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 243 | #if SEPARATE_CODE_AND_RODATA |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 244 | #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 245 | BL_CODE_BASE, \ |
| 246 | BL_CODE_END - BL_CODE_BASE, \ |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 247 | MT_CODE | MT_SECURE), \ |
| 248 | MAP_REGION_FLAT( \ |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 249 | BL_RO_DATA_BASE, \ |
| 250 | BL_RO_DATA_END \ |
| 251 | - BL_RO_DATA_BASE, \ |
| 252 | MT_RO_DATA | MT_SECURE) |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 253 | #else |
| 254 | #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ |
| 255 | BL_CODE_BASE, \ |
| 256 | BL_CODE_END - BL_CODE_BASE, \ |
| 257 | MT_CODE | MT_SECURE) |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 258 | #endif |
| 259 | #if USE_COHERENT_MEM |
| 260 | #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ |
| 261 | BL_COHERENT_RAM_BASE, \ |
| 262 | BL_COHERENT_RAM_END \ |
| 263 | - BL_COHERENT_RAM_BASE, \ |
| 264 | MT_DEVICE | MT_RW | MT_SECURE) |
| 265 | #endif |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 266 | #if USE_ROMLIB |
| 267 | #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ |
| 268 | ROMLIB_RO_BASE, \ |
| 269 | ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ |
| 270 | MT_CODE | MT_SECURE) |
| 271 | |
| 272 | #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ |
| 273 | ROMLIB_RW_BASE, \ |
| 274 | ROMLIB_RW_END - ROMLIB_RW_BASE,\ |
| 275 | MT_MEMORY | MT_RW | MT_SECURE) |
| 276 | #endif |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 277 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 278 | /* |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 279 | * Map mem_protect flash region with read and write permissions |
| 280 | */ |
| 281 | #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ |
| 282 | V2M_FLASH_BLOCK_SIZE, \ |
| 283 | MT_DEVICE | MT_RW | MT_SECURE) |
| 284 | |
| 285 | /* |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 286 | * The max number of regions like RO(code), coherent and data required by |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 287 | * different BL stages which need to be mapped in the MMU. |
| 288 | */ |
Daniel Boulby | b1b058d | 2018-09-18 11:52:49 +0100 | [diff] [blame] | 289 | #define ARM_BL_REGIONS 5 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 290 | |
| 291 | #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ |
| 292 | ARM_BL_REGIONS) |
| 293 | |
| 294 | /* Memory mapped Generic timer interfaces */ |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 295 | #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) |
| 296 | #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) |
| 297 | #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) |
| 298 | #define ARM_SYS_CNT_BASE_S UL(0x2a820000) |
| 299 | #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 300 | |
| 301 | #define ARM_CONSOLE_BAUDRATE 115200 |
| 302 | |
Juan Castillo | b6132f1 | 2015-10-06 14:01:35 +0100 | [diff] [blame] | 303 | /* Trusted Watchdog constants */ |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 304 | #define ARM_SP805_TWDG_BASE UL(0x2a490000) |
Juan Castillo | b6132f1 | 2015-10-06 14:01:35 +0100 | [diff] [blame] | 305 | #define ARM_SP805_TWDG_CLK_HZ 32768 |
| 306 | /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 |
| 307 | * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ |
| 308 | #define ARM_TWDG_TIMEOUT_SEC 128 |
| 309 | #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ |
| 310 | ARM_TWDG_TIMEOUT_SEC) |
| 311 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 312 | /****************************************************************************** |
| 313 | * Required platform porting definitions common to all ARM standard platforms |
| 314 | *****************************************************************************/ |
| 315 | |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 316 | /* |
| 317 | * We need to access DRAM2 from BL2 for PSCI_MEM_PROTECT for |
| 318 | * AArch64 builds |
| 319 | */ |
| 320 | #ifdef AARCH64 |
David Cunado | c150312 | 2018-02-16 21:12:58 +0000 | [diff] [blame] | 321 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) |
| 322 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 323 | #else |
David Cunado | c150312 | 2018-02-16 21:12:58 +0000 | [diff] [blame] | 324 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 325 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 326 | #endif |
| 327 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 328 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 329 | /* |
| 330 | * This macro defines the deepest retention state possible. A higher state |
| 331 | * id will represent an invalid or a power down state. |
| 332 | */ |
| 333 | #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET |
| 334 | |
| 335 | /* |
| 336 | * This macro defines the deepest power down states possible. Any state ID |
| 337 | * higher than this is invalid. |
| 338 | */ |
| 339 | #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF |
| 340 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 341 | /* |
| 342 | * Some data must be aligned on the biggest cache line size in the platform. |
| 343 | * This is known only to the platform as it might have a combination of |
| 344 | * integrated and external caches. |
| 345 | */ |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 346 | #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 347 | |
Soby Mathew | 7c6df5b | 2018-01-15 14:43:42 +0000 | [diff] [blame] | 348 | /* |
| 349 | * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base |
| 350 | * and limit. Leave enough space of BL2 meminfo. |
| 351 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 352 | #define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) |
| 353 | #define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 354 | |
| 355 | /******************************************************************************* |
| 356 | * BL1 specific defines. |
| 357 | * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of |
| 358 | * addresses. |
| 359 | ******************************************************************************/ |
| 360 | #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE |
| 361 | #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 362 | + (PLAT_ARM_TRUSTED_ROM_SIZE - \ |
| 363 | PLAT_ARM_MAX_ROMLIB_RO_SIZE)) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 364 | /* |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 365 | * Put BL1 RW at the top of the Trusted SRAM. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 366 | */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 367 | #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ |
| 368 | ARM_BL_RAM_SIZE - \ |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 369 | (PLAT_ARM_MAX_BL1_RW_SIZE +\ |
| 370 | PLAT_ARM_MAX_ROMLIB_RW_SIZE)) |
| 371 | #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ |
| 372 | (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) |
| 373 | |
| 374 | #define ROMLIB_RO_BASE BL1_RO_LIMIT |
| 375 | #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) |
| 376 | |
| 377 | #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) |
| 378 | #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 379 | |
| 380 | /******************************************************************************* |
| 381 | * BL2 specific defines. |
| 382 | ******************************************************************************/ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 383 | #if BL2_AT_EL3 |
Dimitris Papastamos | 2583649 | 2018-06-11 11:07:58 +0100 | [diff] [blame] | 384 | /* Put BL2 towards the middle of the Trusted SRAM */ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 385 | #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ |
Dimitris Papastamos | 2583649 | 2018-06-11 11:07:58 +0100 | [diff] [blame] | 386 | (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) |
Roberto Vargas | 5220780 | 2017-11-17 13:22:18 +0000 | [diff] [blame] | 387 | #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
| 388 | |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 389 | #else |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 390 | /* |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 391 | * Put BL2 just below BL1. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 392 | */ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 393 | #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) |
| 394 | #define BL2_LIMIT BL1_RW_BASE |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 395 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 396 | |
| 397 | /******************************************************************************* |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 398 | * BL31 specific defines. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 399 | ******************************************************************************/ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 400 | #if ARM_BL31_IN_DRAM |
| 401 | /* |
| 402 | * Put BL31 at the bottom of TZC secured DRAM |
| 403 | */ |
| 404 | #define BL31_BASE ARM_AP_TZC_DRAM1_BASE |
| 405 | #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ |
| 406 | PLAT_ARM_MAX_BL31_SIZE) |
Qixiang Xu | a5f7281 | 2017-08-31 11:45:32 +0800 | [diff] [blame] | 407 | #elif (RESET_TO_BL31) |
Soby Mathew | 68e6928 | 2018-12-12 14:13:52 +0000 | [diff] [blame] | 408 | /* Ensure Position Independent support (PIE) is enabled for this config.*/ |
| 409 | # if !ENABLE_PIE |
| 410 | # error "BL31 must be a PIE if RESET_TO_BL31=1." |
| 411 | # endif |
Qixiang Xu | a5f7281 | 2017-08-31 11:45:32 +0800 | [diff] [blame] | 412 | /* |
Soby Mathew | 68e6928 | 2018-12-12 14:13:52 +0000 | [diff] [blame] | 413 | * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely |
| 414 | * used for building BL31 when RESET_TO_BL31=1. |
Qixiang Xu | a5f7281 | 2017-08-31 11:45:32 +0800 | [diff] [blame] | 415 | */ |
Soby Mathew | 68e6928 | 2018-12-12 14:13:52 +0000 | [diff] [blame] | 416 | #define BL31_BASE 0x0 |
| 417 | #define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 418 | #else |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 419 | /* Put BL31 below BL2 in the Trusted SRAM.*/ |
| 420 | #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ |
| 421 | - PLAT_ARM_MAX_BL31_SIZE) |
| 422 | #define BL31_PROGBITS_LIMIT BL2_BASE |
Dimitris Papastamos | 2583649 | 2018-06-11 11:07:58 +0100 | [diff] [blame] | 423 | /* |
| 424 | * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is |
| 425 | * because in the BL2_AT_EL3 configuration, BL2 is always resident. |
| 426 | */ |
| 427 | #if BL2_AT_EL3 |
| 428 | #define BL31_LIMIT BL2_BASE |
| 429 | #else |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 430 | #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 431 | #endif |
Dimitris Papastamos | 2583649 | 2018-06-11 11:07:58 +0100 | [diff] [blame] | 432 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 433 | |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 434 | #if defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 435 | /******************************************************************************* |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 436 | * BL32 specific defines for EL3 runtime in AArch32 mode |
| 437 | ******************************************************************************/ |
| 438 | # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 439 | /* |
| 440 | * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding |
| 441 | * the page reserved for fw_configs) to BL32 |
| 442 | */ |
| 443 | # define BL32_BASE ARM_TB_FW_CONFIG_LIMIT |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 444 | # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
| 445 | # else |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 446 | /* Put BL32 below BL2 in the Trusted SRAM.*/ |
| 447 | # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ |
| 448 | - PLAT_ARM_MAX_BL32_SIZE) |
| 449 | # define BL32_PROGBITS_LIMIT BL2_BASE |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 450 | # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
| 451 | # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ |
| 452 | |
| 453 | #else |
| 454 | /******************************************************************************* |
| 455 | * BL32 specific defines for EL3 runtime in AArch64 mode |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 456 | ******************************************************************************/ |
| 457 | /* |
| 458 | * On ARM standard platforms, the TSP can execute from Trusted SRAM, |
| 459 | * Trusted DRAM (if available) or the DRAM region secured by the TrustZone |
| 460 | * controller. |
| 461 | */ |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 462 | # if ENABLE_SPM |
| 463 | # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) |
| 464 | # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) |
| 465 | # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) |
| 466 | # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ |
Antonio Nino Diaz | 7289f92 | 2017-11-09 11:34:09 +0000 | [diff] [blame] | 467 | ARM_AP_TZC_DRAM1_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 468 | # elif ARM_BL31_IN_DRAM |
| 469 | # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 470 | PLAT_ARM_MAX_BL31_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 471 | # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 472 | PLAT_ARM_MAX_BL31_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 473 | # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 474 | PLAT_ARM_MAX_BL31_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 475 | # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 476 | ARM_AP_TZC_DRAM1_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 477 | # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID |
| 478 | # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE |
| 479 | # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 480 | # define TSP_PROGBITS_LIMIT BL31_BASE |
| 481 | # define BL32_BASE ARM_TB_FW_CONFIG_LIMIT |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 482 | # define BL32_LIMIT BL31_BASE |
| 483 | # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID |
| 484 | # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE |
| 485 | # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE |
| 486 | # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE |
| 487 | # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 488 | + (UL(1) << 21)) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 489 | # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID |
| 490 | # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE |
| 491 | # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE |
| 492 | # define BL32_BASE ARM_AP_TZC_DRAM1_BASE |
| 493 | # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 494 | ARM_AP_TZC_DRAM1_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 495 | # else |
| 496 | # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" |
| 497 | # endif |
| 498 | #endif /* AARCH32 || JUNO_AARCH32_EL3_RUNTIME */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 499 | |
Antonio Nino Diaz | 7289f92 | 2017-11-09 11:34:09 +0000 | [diff] [blame] | 500 | /* |
| 501 | * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no |
| 502 | * SPD and no SPM, as they are the only ones that can be used as BL32. |
| 503 | */ |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 504 | #if !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME) |
Antonio Nino Diaz | 7289f92 | 2017-11-09 11:34:09 +0000 | [diff] [blame] | 505 | # if defined(SPD_none) && !ENABLE_SPM |
| 506 | # undef BL32_BASE |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 507 | # endif /* defined(SPD_none) && !ENABLE_SPM */ |
| 508 | #endif /* !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME) */ |
Antonio Nino Diaz | e4fa370 | 2016-04-05 11:38:49 +0100 | [diff] [blame] | 509 | |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 510 | /******************************************************************************* |
| 511 | * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. |
| 512 | ******************************************************************************/ |
| 513 | #define BL2U_BASE BL2_BASE |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 514 | #define BL2U_LIMIT BL2_LIMIT |
| 515 | |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 516 | #define NS_BL2U_BASE ARM_NS_DRAM1_BASE |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 517 | #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 518 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 519 | /* |
| 520 | * ID of the secure physical generic timer interrupt used by the TSP. |
| 521 | */ |
| 522 | #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER |
| 523 | |
| 524 | |
Vikram Kanigiri | d79214c | 2015-09-09 10:52:13 +0100 | [diff] [blame] | 525 | /* |
| 526 | * One cache line needed for bakery locks on ARM platforms |
| 527 | */ |
| 528 | #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) |
| 529 | |
Jeenu Viswambharan | b183745 | 2017-10-24 11:47:13 +0100 | [diff] [blame] | 530 | /* Priority levels for ARM platforms */ |
Jeenu Viswambharan | a5b5b8d | 2018-02-06 12:21:39 +0000 | [diff] [blame] | 531 | #define PLAT_RAS_PRI 0x10 |
Jeenu Viswambharan | b183745 | 2017-10-24 11:47:13 +0100 | [diff] [blame] | 532 | #define PLAT_SDEI_CRITICAL_PRI 0x60 |
| 533 | #define PLAT_SDEI_NORMAL_PRI 0x70 |
| 534 | |
| 535 | /* ARM platforms use 3 upper bits of secure interrupt priority */ |
| 536 | #define ARM_PRI_BITS 3 |
Vikram Kanigiri | d79214c | 2015-09-09 10:52:13 +0100 | [diff] [blame] | 537 | |
Jeenu Viswambharan | a5acc0a | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 538 | /* SGI used for SDEI signalling */ |
| 539 | #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 |
| 540 | |
| 541 | /* ARM SDEI dynamic private event numbers */ |
| 542 | #define ARM_SDEI_DP_EVENT_0 1000 |
| 543 | #define ARM_SDEI_DP_EVENT_1 1001 |
| 544 | #define ARM_SDEI_DP_EVENT_2 1002 |
| 545 | |
| 546 | /* ARM SDEI dynamic shared event numbers */ |
| 547 | #define ARM_SDEI_DS_EVENT_0 2000 |
| 548 | #define ARM_SDEI_DS_EVENT_1 2001 |
| 549 | #define ARM_SDEI_DS_EVENT_2 2002 |
| 550 | |
Jeenu Viswambharan | 6e28446 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 551 | #define ARM_SDEI_PRIVATE_EVENTS \ |
| 552 | SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ |
| 553 | SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ |
| 554 | SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ |
| 555 | SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) |
| 556 | |
| 557 | #define ARM_SDEI_SHARED_EVENTS \ |
| 558 | SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ |
| 559 | SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ |
| 560 | SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) |
| 561 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 562 | #endif /* ARM_DEF_H */ |