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git01.mediatek.com / filogic / atf / 8d1ade665cc7903e6afc7549b568199dcb23392a / . / drivers / staging / renesas / rcar / qos / H3 / qos_init_h3_v11.c
blob: 1f656005067d65c69d9a76fdeb5debf05ceea5ed [file] [log] [blame]
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1/*
2 * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <stdint.h>
8#include <debug.h>
9#include <rcar_def.h>
10#include "../qos_common.h"
11#include "qos_init_h3_v11.h"
12
13#define RCAR_QOS_VERSION "rev.0.37"
14
15#define RCAR_QOS_NONE (3U)
16#define RCAR_QOS_TYPE_DEFAULT (0U)
17
18#define RCAR_DRAM_SPLIT_LINEAR (0U)
19#define RCAR_DRAM_SPLIT_4CH (1U)
20#define RCAR_DRAM_SPLIT_2CH (2U)
21#define RCAR_DRAM_SPLIT_AUTO (3U)
22
23#define RST_BASE (0xE6160000U)
24#define RST_MODEMR (RST_BASE + 0x0060U)
25
26#define RCAR_PWRSR8 (0xE6180340U) /* A3VP_PWRSR0 */
27#define RCAR_PWRONCR8 (0xE618034CU) /* A3VP_PWRONCR */
28#define RCAR_PWRSR9 (0xE6180380U) /* A3VC_PWRSR0 */
29#define RCAR_PWRONCR9 (0xE618038CU) /* A3VC_PWRONCR */
30#define RCAR_PWRSR10 (0xE61803C0U) /* A2VC_PWRSR0 */
31#define RCAR_PWRONCR10 (0xE61803CCU) /* A2VC_PWRONCR */
32
33#define DBSC_BASE (0xE6790000U)
34#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
35#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
36#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
37#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
38#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
39#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
40#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
41#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
42#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
43#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
44#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
45#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
46#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
47#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
48#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
49#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
50#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
51#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
52#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
53#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
54#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
55#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
56#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
57#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
58#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
59#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
60#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
61#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
62#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
63#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
64#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
65#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
66#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
67#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
68#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
69#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
70#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
71#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
72#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
73#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
74#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
75#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
76#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
77#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
78#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
79#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
80#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
81#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
82#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
83#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
84#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
85#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
86#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
87#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
88#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
89#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
90#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
91#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
92#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
93#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
94#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
95#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
96#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
97#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
98#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
99#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
100#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
101#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
102#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
103#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
104#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
105#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
106#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
107#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
108
109#define AXI_BASE (0xE6784000U)
110#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
111#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
112#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
113#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
114#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
115#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
116#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
117#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
118#define ADSPLCR0_SWP (0x0CU)
119
120#define MSTAT_BASE (0xE67E0000U)
121#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
122#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
123#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
124#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
125#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
126#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
127#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
128
129#define RALLOC_BASE (0xE67F0000U)
130#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
131#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
132#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
133#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
134#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
135#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
136#define RALLOC_EC (RALLOC_BASE + 0x003CU)
137#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
138#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
139#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
140#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
141
142#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
143static const mstat_slot_t mstat_fix[] = {
144 {0x0000U, 0x0000000000000000UL},
145 {0x0008U, 0x0000000000000000UL},
146 {0x0010U, 0x0000000000000000UL},
147 {0x0018U, 0x0000000000000000UL},
148 {0x0020U, 0x0000000000000000UL},
149 {0x0028U, 0x0000000000000000UL},
150 {0x0030U, 0x001004030000FFFFUL},
151 {0x0038U, 0x001008060000FFFFUL},
152 {0x0040U, 0x001414090000FFFFUL},
153 {0x0048U, 0x0000000000000000UL},
154 {0x0050U, 0x001410010000FFFFUL},
155 {0x0058U, 0x00140C0C0000FFFFUL},
156 {0x0060U, 0x00140C0C0000FFFFUL},
157 {0x0068U, 0x0000000000000000UL},
158 {0x0070U, 0x001410010000FFFFUL},
159 {0x0078U, 0x001008060000FFFFUL},
160 {0x0080U, 0x001004020000FFFFUL},
161 {0x0088U, 0x001414090000FFFFUL},
162 {0x0090U, 0x00140C0C0000FFFFUL},
163 {0x0098U, 0x001408080000FFFFUL},
164 {0x00A0U, 0x000C08020000FFFFUL},
165 {0x00A8U, 0x000C04010000FFFFUL},
166 {0x00B0U, 0x000C04010000FFFFUL},
167 {0x00B8U, 0x0000000000000000UL},
168 {0x00C0U, 0x000C08020000FFFFUL},
169 {0x00C8U, 0x000C04010000FFFFUL},
170 {0x00D0U, 0x000C04010000FFFFUL},
171 {0x00D8U, 0x000C04030000FFFFUL},
172 {0x00E0U, 0x000C100F0000FFFFUL},
173 {0x00E8U, 0x0000000000000000UL},
174 {0x00F0U, 0x001010080000FFFFUL},
175 {0x00F8U, 0x001010080000FFFFUL},
176 {0x0100U, 0x0000000000000000UL},
177 {0x0108U, 0x000C04030000FFFFUL},
178 {0x0110U, 0x001010080000FFFFUL},
179 {0x0118U, 0x001010080000FFFFUL},
180 {0x0120U, 0x0000000000000000UL},
181 {0x0128U, 0x000C100E0000FFFFUL},
182 {0x0130U, 0x0000000000000000UL},
183 {0x0138U, 0x001008050000FFFFUL},
184 {0x0140U, 0x001008050000FFFFUL},
185 {0x0148U, 0x001008050000FFFFUL},
186 {0x0150U, 0x001008050000FFFFUL},
187 {0x0158U, 0x001008050000FFFFUL},
188 {0x0160U, 0x001008050000FFFFUL},
189 {0x0168U, 0x001008050000FFFFUL},
190 {0x0170U, 0x001008050000FFFFUL},
191 {0x0178U, 0x001004030000FFFFUL},
192 {0x0180U, 0x001004030000FFFFUL},
193 {0x0188U, 0x001004030000FFFFUL},
194 {0x0190U, 0x001014140000FFFFUL},
195 {0x0198U, 0x001014140000FFFFUL},
196 {0x01A0U, 0x001008050000FFFFUL},
197 {0x01A8U, 0x001008050000FFFFUL},
198 {0x01B0U, 0x001008050000FFFFUL},
199 {0x01B8U, 0x0000000000000000UL},
200 {0x01C0U, 0x0000000000000000UL},
201 {0x01C8U, 0x0000000000000000UL},
202 {0x01D0U, 0x0000000000000000UL},
203 {0x01D8U, 0x0000000000000000UL},
204 {0x01E0U, 0x0000000000000000UL},
205 {0x01E8U, 0x0000000000000000UL},
206 {0x01F0U, 0x0000000000000000UL},
207 {0x01F8U, 0x0000000000000000UL},
208 {0x0200U, 0x0000000000000000UL},
209 {0x0208U, 0x0000000000000000UL},
210 {0x0210U, 0x0000000000000000UL},
211 {0x0218U, 0x0000000000000000UL},
212 {0x0220U, 0x0000000000000000UL},
213 {0x0228U, 0x0000000000000000UL},
214 {0x0230U, 0x0000000000000000UL},
215 {0x0238U, 0x0000000000000000UL},
216 {0x0240U, 0x0000000000000000UL},
217 {0x0248U, 0x0000000000000000UL},
218 {0x0250U, 0x0000000000000000UL},
219 {0x0258U, 0x0000000000000000UL},
220 {0x0260U, 0x0000000000000000UL},
221 {0x0268U, 0x001408010000FFFFUL},
222 {0x0270U, 0x001404010000FFFFUL},
223 {0x0278U, 0x0000000000000000UL},
224 {0x0280U, 0x0000000000000000UL},
225 {0x0288U, 0x0000000000000000UL},
226 {0x0290U, 0x001408010000FFFFUL},
227 {0x0298U, 0x001404010000FFFFUL},
228 {0x02A0U, 0x000C04010000FFFFUL},
229 {0x02A8U, 0x000C04010000FFFFUL},
230 {0x02B0U, 0x001404010000FFFFUL},
231 {0x02B8U, 0x0000000000000000UL},
232 {0x02C0U, 0x0000000000000000UL},
233 {0x02C8U, 0x0000000000000000UL},
234 {0x02D0U, 0x000C04010000FFFFUL},
235 {0x02D8U, 0x000C04010000FFFFUL},
236 {0x02E0U, 0x001404010000FFFFUL},
237 {0x02E8U, 0x0000000000000000UL},
238 {0x02F0U, 0x0000000000000000UL},
239 {0x02F8U, 0x0000000000000000UL},
240 {0x0300U, 0x0000000000000000UL},
241 {0x0308U, 0x0000000000000000UL},
242 {0x0310U, 0x0000000000000000UL},
243 {0x0318U, 0x0000000000000000UL},
244 {0x0320U, 0x0000000000000000UL},
245 {0x0328U, 0x0000000000000000UL},
246 {0x0330U, 0x0000000000000000UL},
247 {0x0338U, 0x0000000000000000UL},
248};
249
250static const mstat_slot_t mstat_be[] = {
251 {0x0000U, 0x001200100C89C401UL},
252 {0x0008U, 0x001200100C89C401UL},
253 {0x0010U, 0x001200100C89C401UL},
254 {0x0018U, 0x001200100C89C401UL},
255 {0x0020U, 0x001100100C803401UL},
256 {0x0028U, 0x001100100C80FC01UL},
257 {0x0030U, 0x0000000000000000UL},
258 {0x0038U, 0x0000000000000000UL},
259 {0x0040U, 0x0000000000000000UL},
260 {0x0048U, 0x0000000000000000UL},
261 {0x0050U, 0x0000000000000000UL},
262 {0x0058U, 0x0000000000000000UL},
263 {0x0060U, 0x0000000000000000UL},
264 {0x0068U, 0x001100100C803401UL},
265 {0x0070U, 0x0000000000000000UL},
266 {0x0078U, 0x0000000000000000UL},
267 {0x0080U, 0x0000000000000000UL},
268 {0x0088U, 0x0000000000000000UL},
269 {0x0090U, 0x0000000000000000UL},
270 {0x0098U, 0x0000000000000000UL},
271 {0x00A0U, 0x0000000000000000UL},
272 {0x00A8U, 0x0000000000000000UL},
273 {0x00B0U, 0x0000000000000000UL},
274 {0x00B8U, 0x001100100C803401UL},
275 {0x00C0U, 0x0000000000000000UL},
276 {0x00C8U, 0x0000000000000000UL},
277 {0x00D0U, 0x0000000000000000UL},
278 {0x00D8U, 0x0000000000000000UL},
279 {0x00E0U, 0x0000000000000000UL},
280 {0x00E8U, 0x001100100C803401UL},
281 {0x00F0U, 0x0000000000000000UL},
282 {0x00F8U, 0x0000000000000000UL},
283 {0x0100U, 0x0000000000000000UL},
284 {0x0108U, 0x0000000000000000UL},
285 {0x0110U, 0x0000000000000000UL},
286 {0x0118U, 0x0000000000000000UL},
287 {0x0120U, 0x0000000000000000UL},
288 {0x0128U, 0x0000000000000000UL},
289 {0x0130U, 0x001100100C803401UL},
290 {0x0138U, 0x0000000000000000UL},
291 {0x0140U, 0x0000000000000000UL},
292 {0x0148U, 0x0000000000000000UL},
293 {0x0150U, 0x0000000000000000UL},
294 {0x0158U, 0x0000000000000000UL},
295 {0x0160U, 0x0000000000000000UL},
296 {0x0168U, 0x0000000000000000UL},
297 {0x0170U, 0x0000000000000000UL},
298 {0x0178U, 0x0000000000000000UL},
299 {0x0180U, 0x0000000000000000UL},
300 {0x0188U, 0x0000000000000000UL},
301 {0x0190U, 0x0000000000000000UL},
302 {0x0198U, 0x0000000000000000UL},
303 {0x01A0U, 0x0000000000000000UL},
304 {0x01A8U, 0x0000000000000000UL},
305 {0x01B0U, 0x0000000000000000UL},
306 {0x01B8U, 0x001100100C803401UL},
307 {0x01C0U, 0x001100800C8FFC01UL},
308 {0x01C8U, 0x001100800C8FFC01UL},
309 {0x01D0U, 0x001100800C8FFC01UL},
310 {0x01D8U, 0x001100800C8FFC01UL},
311 {0x01E0U, 0x001100100C80FC01UL},
312 {0x01E8U, 0x001200100C80FC01UL},
313 {0x01F0U, 0x001100100C80FC01UL},
314 {0x01F8U, 0x001100100C803401UL},
315 {0x0200U, 0x001100100C80FC01UL},
316 {0x0208U, 0x001200100C80FC01UL},
317 {0x0210U, 0x001100100C80FC01UL},
318 {0x0218U, 0x001100100C825801UL},
319 {0x0220U, 0x001100100C825801UL},
320 {0x0228U, 0x001100100C803401UL},
321 {0x0230U, 0x001100100C825801UL},
322 {0x0238U, 0x001100100C825801UL},
323 {0x0240U, 0x001200100C8BB801UL},
324 {0x0248U, 0x001100200C8FFC01UL},
325 {0x0250U, 0x001200100C8BB801UL},
326 {0x0258U, 0x001100200C8FFC01UL},
327 {0x0260U, 0x001100100C84E401UL},
328 {0x0268U, 0x0000000000000000UL},
329 {0x0270U, 0x0000000000000000UL},
330 {0x0278U, 0x001100100C81F401UL},
331 {0x0280U, 0x001100100C803401UL},
332 {0x0288U, 0x001100100C803401UL},
333 {0x0290U, 0x0000000000000000UL},
334 {0x0298U, 0x0000000000000000UL},
335 {0x02A0U, 0x0000000000000000UL},
336 {0x02A8U, 0x0000000000000000UL},
337 {0x02B0U, 0x0000000000000000UL},
338 {0x02B8U, 0x001100100C803401UL},
339 {0x02C0U, 0x001100100C803401UL},
340 {0x02C8U, 0x001100100C803401UL},
341 {0x02D0U, 0x0000000000000000UL},
342 {0x02D8U, 0x0000000000000000UL},
343 {0x02E0U, 0x0000000000000000UL},
344 {0x02E8U, 0x001100100C803401UL},
345 {0x02F0U, 0x001100300C8FFC01UL},
346 {0x02F8U, 0x001100500C8FFC01UL},
347 {0x0300U, 0x001100100C803401UL},
348 {0x0308U, 0x001100300C8FFC01UL},
349 {0x0310U, 0x001100500C8FFC01UL},
350 {0x0318U, 0x001200100C803401UL},
351 {0x0320U, 0x001100300C8FFC01UL},
352 {0x0328U, 0x001100500C8FFC01UL},
353 {0x0330U, 0x001100300C8FFC01UL},
354 {0x0338U, 0x001100500C8FFC01UL},
355};
356#endif
357
358static void dbsc_setting(void)
359{
360 uint32_t md = 0;
361
362 /* BUFCAM settings */
363 /* DBSC_DBCAM0CNF0 not set */
364 io_write_32(DBSC_DBCAM0CNF1, 0x00044218); /* dbcam0cnf1 */
365 io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */
366 /* DBSC_DBCAM0CNF3 not set */
367 io_write_32(DBSC_DBSCHCNT0, 0x080F0037); /* dbschcnt0 */
368 io_write_32(DBSC_DBSCHCNT1, 0x00001010); /* dbschcnt1 */
369 io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */
370 io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */
371
372 md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
373
374 switch (md) {
375 case 0x0:
376 /* DDR3200 */
377 io_write_32(DBSC_SCFCTST2, 0x012F1123);
378 break;
379 case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
380 /* DDR2800 */
381 io_write_32(DBSC_SCFCTST2, 0x012F1123);
382 break;
383 case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
384 /* DDR2400 */
385 io_write_32(DBSC_SCFCTST2, 0x012F1123);
386 break;
387 default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
388 /* DDR1600 */
389 io_write_32(DBSC_SCFCTST2, 0x012F1123);
390 break;
391 }
392
393 /* QoS Settings */
394 io_write_32(DBSC_DBSCHQOS_0_0, 0x0000F000);
395 io_write_32(DBSC_DBSCHQOS_0_1, 0x0000E000);
396 io_write_32(DBSC_DBSCHQOS_0_2, 0x00007000);
397 io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
398 /* DBSC_DBSCHQOS_1_0 not set */
399 /* DBSC_DBSCHQOS_1_1 not set */
400 /* DBSC_DBSCHQOS_1_2 not set */
401 /* DBSC_DBSCHQOS_1_3 not set */
402 /* DBSC_DBSCHQOS_2_0 not set */
403 /* DBSC_DBSCHQOS_2_1 not set */
404 /* DBSC_DBSCHQOS_2_2 not set */
405 /* DBSC_DBSCHQOS_2_3 not set */
406 /* DBSC_DBSCHQOS_3_0 not set */
407 /* DBSC_DBSCHQOS_3_1 not set */
408 /* DBSC_DBSCHQOS_3_2 not set */
409 /* DBSC_DBSCHQOS_3_3 not set */
410 io_write_32(DBSC_DBSCHQOS_4_0, 0x00000E00);
411 io_write_32(DBSC_DBSCHQOS_4_1, 0x00000DFF);
412 io_write_32(DBSC_DBSCHQOS_4_2, 0x00000400);
413 io_write_32(DBSC_DBSCHQOS_4_3, 0x00000200);
414 /* DBSC_DBSCHQOS_5_0 not set */
415 /* DBSC_DBSCHQOS_5_1 not set */
416 /* DBSC_DBSCHQOS_5_2 not set */
417 /* DBSC_DBSCHQOS_5_3 not set */
418 /* DBSC_DBSCHQOS_6_0 not set */
419 /* DBSC_DBSCHQOS_6_1 not set */
420 /* DBSC_DBSCHQOS_6_2 not set */
421 /* DBSC_DBSCHQOS_6_3 not set */
422 /* DBSC_DBSCHQOS_7_0 not set */
423 /* DBSC_DBSCHQOS_7_1 not set */
424 /* DBSC_DBSCHQOS_7_2 not set */
425 /* DBSC_DBSCHQOS_7_3 not set */
426 /* DBSC_DBSCHQOS_8_0 not set */
427 /* DBSC_DBSCHQOS_8_1 not set */
428 /* DBSC_DBSCHQOS_8_2 not set */
429 /* DBSC_DBSCHQOS_8_3 not set */
430 io_write_32(DBSC_DBSCHQOS_9_0, 0x00000C00);
431 io_write_32(DBSC_DBSCHQOS_9_1, 0x00000BFF);
432 io_write_32(DBSC_DBSCHQOS_9_2, 0x00000400);
433 io_write_32(DBSC_DBSCHQOS_9_3, 0x00000200);
434 /* DBSC_DBSCHQOS_10_0 not set */
435 /* DBSC_DBSCHQOS_10_1 not set */
436 /* DBSC_DBSCHQOS_10_2 not set */
437 /* DBSC_DBSCHQOS_10_3 not set */
438 /* DBSC_DBSCHQOS_11_0 not set */
439 /* DBSC_DBSCHQOS_11_1 not set */
440 /* DBSC_DBSCHQOS_11_2 not set */
441 /* DBSC_DBSCHQOS_11_3 not set */
442 /* DBSC_DBSCHQOS_12_0 not set */
443 /* DBSC_DBSCHQOS_12_1 not set */
444 /* DBSC_DBSCHQOS_12_2 not set */
445 /* DBSC_DBSCHQOS_12_3 not set */
446 io_write_32(DBSC_DBSCHQOS_13_0, 0x00000980);
447 io_write_32(DBSC_DBSCHQOS_13_1, 0x0000097F);
448 io_write_32(DBSC_DBSCHQOS_13_2, 0x00000300);
449 io_write_32(DBSC_DBSCHQOS_13_3, 0x00000180);
450 io_write_32(DBSC_DBSCHQOS_14_0, 0x00000800);
451 io_write_32(DBSC_DBSCHQOS_14_1, 0x000007FF);
452 io_write_32(DBSC_DBSCHQOS_14_2, 0x00000300);
453 io_write_32(DBSC_DBSCHQOS_14_3, 0x00000180);
454 io_write_32(DBSC_DBSCHQOS_15_0, 0x000007D0);
455 io_write_32(DBSC_DBSCHQOS_15_1, 0x000007CF);
456 io_write_32(DBSC_DBSCHQOS_15_2, 0x000005D0);
457 io_write_32(DBSC_DBSCHQOS_15_3, 0x000003D0);
458}
459
460void qos_init_h3_v11(void)
461{
462 dbsc_setting();
463
464 /* DRAM Split Address mapping */
465#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
466 (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
467 NOTICE("BL2: DRAM Split is 4ch\n");
468 io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
469 | ADSPLCR0_SPLITSEL(0xFFU)
470 | ADSPLCR0_AREA(0x1BU)
471 | ADSPLCR0_SWP);
472 io_write_32(AXI_ADSPLCR1, 0x00000000U);
473 io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
474 io_write_32(AXI_ADSPLCR3, 0x00000000U);
475#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
476 NOTICE("BL2: DRAM Split is 2ch\n");
477 io_write_32(AXI_ADSPLCR0, 0x00000000U);
478 io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
479 | ADSPLCR0_SPLITSEL(0xFFU)
480 | ADSPLCR0_AREA(0x1BU)
481 | ADSPLCR0_SWP);
482 io_write_32(AXI_ADSPLCR2, 0x00000000U);
483 io_write_32(AXI_ADSPLCR3, 0x00000000U);
484#else
485 NOTICE("BL2: DRAM Split is OFF\n");
486#endif
487
488#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
489#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
490 NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
491#endif
492
493 /* AR Cache setting */
494 io_write_32(0xE67D1000U, 0x00000100U);
495 io_write_32(0xE67D1008U, 0x00000100U);
496
497 /* Resource Alloc setting */
498#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
499 io_write_32(RALLOC_RAS, 0x00000020U);
500#else
501 io_write_32(RALLOC_RAS, 0x00000040U);
502#endif
503 io_write_32(RALLOC_FIXTH, 0x000F0005U);
504 io_write_32(RALLOC_REGGD, 0x00000000U);
505#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
506 io_write_64(RALLOC_DANN, 0x0101010102020201UL);
507 io_write_32(RALLOC_DANT, 0x00181008U);
508#else
509 io_write_64(RALLOC_DANN, 0x0101000004040401UL);
510 io_write_32(RALLOC_DANT, 0x003C2010U);
511#endif
512 io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
513 io_write_64(RALLOC_EMS, 0x0000000000000000UL);
514 io_write_32(RALLOC_INSFC, 0xC7840001U);
515 io_write_32(RALLOC_BERR, 0x00000000U);
516 io_write_32(RALLOC_RACNT0, 0x00000000U);
517
518 /* MSTAT setting */
519 io_write_32(MSTAT_SL_INIT,
520 SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
521 io_write_32(MSTAT_REF_ARS, 0x00330000U);
522
523 /* MSTAT SRAM setting */
524 {
525 uint32_t i;
526
527 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
528 io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
529 mstat_fix[i].value);
530 io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
531 mstat_fix[i].value);
532 }
533 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
534 io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
535 mstat_be[i].value);
536 io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
537 mstat_be[i].value);
538 }
539 }
540
541 /* 3DG bus Leaf setting */
542 io_write_32(0xFD820808U, 0x00001234U);
543 io_write_32(0xFD820800U, 0x0000003FU);
544 io_write_32(0xFD821800U, 0x0000003FU);
545 io_write_32(0xFD822800U, 0x0000003FU);
546 io_write_32(0xFD823800U, 0x0000003FU);
547 io_write_32(0xFD824800U, 0x0000003FU);
548 io_write_32(0xFD825800U, 0x0000003FU);
549 io_write_32(0xFD826800U, 0x0000003FU);
550 io_write_32(0xFD827800U, 0x0000003FU);
551
552 /* VIO bus Leaf setting */
553 io_write_32(0xFEB89800, 0x00000001U);
554 io_write_32(0xFEB8A800, 0x00000001U);
555 io_write_32(0xFEB8B800, 0x00000001U);
556 io_write_32(0xFEB8C800, 0x00000001U);
557
558 /* HSC bus Leaf setting */
559 io_write_32(0xE6430800, 0x00000001U);
560 io_write_32(0xE6431800, 0x00000001U);
561 io_write_32(0xE6432800, 0x00000001U);
562 io_write_32(0xE6433800, 0x00000001U);
563
564 /* MP bus Leaf setting */
565 io_write_32(0xEC620800, 0x00000001U);
566 io_write_32(0xEC621800, 0x00000001U);
567
568 /* PERIE bus Leaf setting */
569 io_write_32(0xE7760800, 0x00000001U);
570 io_write_32(0xE7768800, 0x00000001U);
571
572 /* PERIW bus Leaf setting */
573 io_write_32(0xE6760800, 0x00000001U);
574 io_write_32(0xE6768800, 0x00000001U);
575
576 /* RT bus Leaf setting */
577 io_write_32(0xFFC50800, 0x00000001U);
578 io_write_32(0xFFC51800, 0x00000001U);
579
580 /* CCI bus Leaf setting */
581 {
582
583 uint32_t modemr = io_read_32(RCAR_MODEMR);
584
585 modemr &= MODEMR_BOOT_CPU_MASK;
586
587 if ((modemr == MODEMR_BOOT_CPU_CA57) ||
588 (modemr == MODEMR_BOOT_CPU_CA53)) {
589 io_write_32(0xF1300800, 0x00000001U);
590 io_write_32(0xF1340800, 0x00000001U);
591 io_write_32(0xF1380800, 0x00000001U);
592 io_write_32(0xF13C0800, 0x00000001U);
593 }
594 }
595
596 /* Resource Alloc start */
597 io_write_32(RALLOC_RAEN, 0x00000001U);
598
599 /* MSTAT start */
600 io_write_32(MSTAT_STATQC, 0x00000001U);
601#else
602 NOTICE("BL2: QoS is None\n");
603
604 /* Resource Alloc setting */
605 io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
606#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
607}