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Antonio Nino Diazc326c342019-01-11 11:20:10 +00001/*
Govindraj Raja24d3a4e2023-12-21 13:57:49 -06002 * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
Antonio Nino Diazc326c342019-01-11 11:20:10 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef ARCH_FEATURES_H
8#define ARCH_FEATURES_H
9
10#include <stdbool.h>
11
12#include <arch_helpers.h>
Andre Przywarae8920f62022-11-10 14:28:01 +000013#include <common/feat_detect.h>
Antonio Nino Diazc326c342019-01-11 11:20:10 +000014
Andre Przywarabb0db3b2023-01-25 12:26:14 +000015#define ISOLATE_FIELD(reg, feat) \
Andre Przywara0dda4242023-04-18 16:58:36 +010016 ((unsigned int)(((reg) >> (feat)) & ID_REG_FIELD_MASK))
Andre Przywarabb0db3b2023-01-25 12:26:14 +000017
Andre Przywara0dda4242023-04-18 16:58:36 +010018#define CREATE_FEATURE_FUNCS_VER(name, read_func, idvalue, guard) \
19static inline bool is_ ## name ## _supported(void) \
20{ \
21 if ((guard) == FEAT_STATE_DISABLED) { \
22 return false; \
23 } \
24 if ((guard) == FEAT_STATE_ALWAYS) { \
25 return true; \
26 } \
27 return read_func() >= (idvalue); \
Antonio Nino Diazd29d21e2019-02-06 09:23:04 +000028}
29
Andre Przywara0dda4242023-04-18 16:58:36 +010030#define CREATE_FEATURE_FUNCS(name, idreg, idfield, guard) \
31static unsigned int read_ ## name ## _id_field(void) \
32{ \
33 return ISOLATE_FIELD(read_ ## idreg(), idfield); \
34} \
35CREATE_FEATURE_FUNCS_VER(name, read_ ## name ## _id_field, 1U, guard)
Andre Przywara97272942023-01-26 15:27:38 +000036
Andre Przywara0dda4242023-04-18 16:58:36 +010037static inline bool is_armv7_gentimer_present(void)
Andre Przywara98908b32022-11-17 16:42:09 +000038{
Andre Przywara0dda4242023-04-18 16:58:36 +010039 /* The Generic Timer is always present in an ARMv8-A implementation */
40 return true;
Andre Przywara98908b32022-11-17 16:42:09 +000041}
42
Andre Przywara0dda4242023-04-18 16:58:36 +010043CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT,
44 ENABLE_FEAT_PAN)
45CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT,
46 ENABLE_FEAT_VHE)
Daniel Boulby44b43332020-11-25 16:36:46 +000047
Antonio Nino Diazc326c342019-01-11 11:20:10 +000048static inline bool is_armv8_2_ttcnp_present(void)
49{
50 return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) &
51 ID_AA64MMFR2_EL1_CNP_MASK) != 0U;
52}
53
Juan Pablo Condee089a172022-06-29 17:44:43 -040054static inline bool is_feat_pacqarma3_present(void)
55{
56 uint64_t mask_id_aa64isar2 =
57 (ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) |
58 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT);
59
60 /* If any of the fields is not zero, QARMA3 algorithm is present */
61 return (read_id_aa64isar2_el1() & mask_id_aa64isar2) != 0U;
62}
63
Antonio Nino Diaz25cda672019-02-19 11:53:51 +000064static inline bool is_armv8_3_pauth_present(void)
65{
Juan Pablo Condee089a172022-06-29 17:44:43 -040066 uint64_t mask_id_aa64isar1 =
67 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) |
68 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) |
69 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) |
70 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT);
Antonio Nino Diaz25cda672019-02-19 11:53:51 +000071
Juan Pablo Condee089a172022-06-29 17:44:43 -040072 /*
73 * If any of the fields is not zero or QARMA3 is present,
74 * PAuth is present
75 */
76 return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U ||
77 is_feat_pacqarma3_present());
Antonio Nino Diaz25cda672019-02-19 11:53:51 +000078}
79
Sathees Balya74155972019-01-25 11:36:01 +000080static inline bool is_armv8_4_ttst_present(void)
81{
82 return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) &
83 ID_AA64MMFR2_EL1_ST_MASK) == 1U;
84}
85
Alexei Fedorov90f2e882019-05-24 12:17:09 +010086static inline bool is_armv8_5_bti_present(void)
87{
88 return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_BT_SHIFT) &
89 ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED;
90}
91
Govindraj Raja24d3a4e2023-12-21 13:57:49 -060092CREATE_FEATURE_FUNCS(feat_mte, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT,
93 ENABLE_FEAT_MTE)
Govindraj Rajad7b63ac2024-01-26 10:08:37 -060094CREATE_FEATURE_FUNCS_VER(feat_mte2, read_feat_mte_id_field, MTE_IMPLEMENTED_ELX,
95 ENABLE_FEAT_MTE2)
Andre Przywara0dda4242023-04-18 16:58:36 +010096CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT,
97 ENABLE_FEAT_SEL2)
98CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT,
99 ENABLE_FEAT_TWED)
100CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
101 ENABLE_FEAT_FGT)
102CREATE_FEATURE_FUNCS(feat_mte_perm, id_aa64pfr2_el1,
103 ID_AA64PFR2_EL1_MTEPERM_SHIFT, ENABLE_FEAT_MTE_PERM)
104CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
105 ENABLE_FEAT_ECV)
106CREATE_FEATURE_FUNCS_VER(feat_ecv_v2, read_feat_ecv_id_field,
107 ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV)
Mark Brownc37eee72023-03-14 20:13:03 +0000108
Andre Przywara0dda4242023-04-18 16:58:36 +0100109CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT,
110 ENABLE_FEAT_RNG)
111CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT,
112 ENABLE_FEAT_TCR2)
Mark Brown293a6612023-03-14 20:48:43 +0000113
Andre Przywara0dda4242023-04-18 16:58:36 +0100114CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT,
115 ENABLE_FEAT_S2POE)
116CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT,
117 ENABLE_FEAT_S1POE)
Mark Brown293a6612023-03-14 20:48:43 +0000118static inline bool is_feat_sxpoe_supported(void)
119{
120 return is_feat_s1poe_supported() || is_feat_s2poe_supported();
121}
122
Andre Przywara0dda4242023-04-18 16:58:36 +0100123CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT,
124 ENABLE_FEAT_S2PIE)
125CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT,
126 ENABLE_FEAT_S1PIE)
Mark Brown293a6612023-03-14 20:48:43 +0000127static inline bool is_feat_sxpie_supported(void)
128{
129 return is_feat_s1pie_supported() || is_feat_s2pie_supported();
130}
131
Andre Przywara0dda4242023-04-18 16:58:36 +0100132/* FEAT_GCS: Guarded Control Stack */
133CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT,
134 ENABLE_FEAT_GCS)
Andre Przywara2c550e32022-11-10 14:41:07 +0000135
Andre Przywara0dda4242023-04-18 16:58:36 +0100136/* FEAT_AMU: Activity Monitors Extension */
137CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
138 ENABLE_FEAT_AMU)
139CREATE_FEATURE_FUNCS_VER(feat_amuv1p1, read_feat_amu_id_field,
140 ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
johpow01fa59c6f2020-10-02 13:41:11 -0500141
Alexei Fedorov19933552020-05-26 13:16:41 +0100142/*
143 * Return MPAM version:
144 *
145 * 0x00: None Armv8.0 or later
146 * 0x01: v0.1 Armv8.4 or later
147 * 0x10: v1.0 Armv8.2 or later
148 * 0x11: v1.1 Armv8.4 or later
149 *
150 */
Andre Przywara84b86532022-11-17 16:42:09 +0000151static inline unsigned int read_feat_mpam_version(void)
Alexei Fedorov19933552020-05-26 13:16:41 +0100152{
153 return (unsigned int)((((read_id_aa64pfr0_el1() >>
154 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) |
155 ((read_id_aa64pfr1_el1() >>
156 ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
157}
158
Andre Przywara0dda4242023-04-18 16:58:36 +0100159CREATE_FEATURE_FUNCS_VER(feat_mpam, read_feat_mpam_version, 1U,
Arvind Ram Prakashab28d4b2023-10-11 12:10:56 -0500160 ENABLE_FEAT_MPAM)
Andre Przywaraf20ad902022-11-15 11:45:19 +0000161
Andre Przywara0dda4242023-04-18 16:58:36 +0100162/* FEAT_HCX: Extended Hypervisor Configuration Register */
163CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT,
164 ENABLE_FEAT_HCX)
johpow01f91e59f2021-08-04 19:38:18 -0500165
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400166static inline bool is_feat_rng_trap_present(void)
167{
168 return (((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT) &
169 ID_AA64PFR1_EL1_RNDR_TRAP_MASK)
170 == ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED);
171}
172
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500173static inline unsigned int get_armv9_2_feat_rme_support(void)
174{
175 /*
176 * Return the RME version, zero if not supported. This function can be
177 * used as both an integer value for the RME version or compared to zero
178 * to detect RME presence.
179 */
180 return (unsigned int)(read_id_aa64pfr0_el1() >>
181 ID_AA64PFR0_FEAT_RME_SHIFT) & ID_AA64PFR0_FEAT_RME_MASK;
182}
183
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000184/*********************************************************************************
185 * Function to identify the presence of FEAT_SB (Speculation Barrier Instruction)
186 ********************************************************************************/
Andre Przywara46880dc2022-11-17 16:42:09 +0000187static inline unsigned int read_feat_sb_id_field(void)
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000188{
Andre Przywara0dda4242023-04-18 16:58:36 +0100189 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT);
Andre Przywara06ea44e2022-11-17 17:30:43 +0000190}
191
Sona Mathew3b84c962023-10-25 16:48:19 -0500192/*
193 * FEAT_CSV2: Cache Speculation Variant 2. This checks bit fields[56-59]
194 * of id_aa64pfr0_el1 register and can be used to check for below features:
195 * FEAT_CSV2_2: Cache Speculation Variant CSV2_2.
196 * FEAT_CSV2_3: Cache Speculation Variant CSV2_3.
197 * 0b0000 - Feature FEAT_CSV2 is not implemented.
198 * 0b0001 - Feature FEAT_CSV2 is implemented, but FEAT_CSV2_2 and FEAT_CSV2_3
199 * are not implemented.
200 * 0b0010 - Feature FEAT_CSV2_2 is implemented but FEAT_CSV2_3 is not
201 * implemented.
202 * 0b0011 - Feature FEAT_CSV2_3 is implemented.
203 */
204static inline unsigned int read_feat_csv2_id_field(void)
205{
206 return (unsigned int)(read_id_aa64pfr0_el1() >>
207 ID_AA64PFR0_CSV2_SHIFT) & ID_AA64PFR0_CSV2_MASK;
208}
209
Andre Przywara0dda4242023-04-18 16:58:36 +0100210CREATE_FEATURE_FUNCS_VER(feat_csv2_2, read_feat_csv2_id_field,
211 ID_AA64PFR0_CSV2_2_SUPPORTED, ENABLE_FEAT_CSV2_2)
Sona Mathew3b84c962023-10-25 16:48:19 -0500212CREATE_FEATURE_FUNCS_VER(feat_csv2_3, read_feat_csv2_id_field,
213 ID_AA64PFR0_CSV2_3_SUPPORTED, ENABLE_FEAT_CSV2_3)
Andre Przywara06ea44e2022-11-17 17:30:43 +0000214
Andre Przywara0dda4242023-04-18 16:58:36 +0100215/* FEAT_SPE: Statistical Profiling Extension */
216CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT,
217 ENABLE_SPE_FOR_NS)
Andre Przywara06ea44e2022-11-17 17:30:43 +0000218
Andre Przywara0dda4242023-04-18 16:58:36 +0100219/* FEAT_SVE: Scalable Vector Extension */
220CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT,
221 ENABLE_SVE_FOR_NS)
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000222
Andre Przywara0dda4242023-04-18 16:58:36 +0100223/* FEAT_RAS: Reliability, Accessibility, Serviceability */
224CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1,
225 ID_AA64PFR0_RAS_SHIFT, ENABLE_FEAT_RAS)
Andre Przywaraedc449d2023-01-27 14:09:20 +0000226
Andre Przywara0dda4242023-04-18 16:58:36 +0100227/* FEAT_DIT: Data Independent Timing instructions */
228CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1,
229 ID_AA64PFR0_DIT_SHIFT, ENABLE_FEAT_DIT)
Andre Przywaraedc449d2023-01-27 14:09:20 +0000230
Andre Przywara0dda4242023-04-18 16:58:36 +0100231CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1,
232 ID_AA64DFR0_TRACEVER_SHIFT, ENABLE_SYS_REG_TRACE_FOR_NS)
Andre Przywaraedc449d2023-01-27 14:09:20 +0000233
Andre Przywara0dda4242023-04-18 16:58:36 +0100234/* FEAT_TRF: TraceFilter */
235CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT,
236 ENABLE_TRF_FOR_NS)
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000237
Andre Przywara0dda4242023-04-18 16:58:36 +0100238/* FEAT_NV2: Enhanced Nested Virtualization */
239CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 0)
240CREATE_FEATURE_FUNCS_VER(feat_nv2, read_feat_nv_id_field,
241 ID_AA64MMFR2_EL1_NV2_SUPPORTED, CTX_INCLUDE_NEVE_REGS)
Andre Przywarac97c5512022-11-17 16:42:09 +0000242
Andre Przywara0dda4242023-04-18 16:58:36 +0100243/* FEAT_BRBE: Branch Record Buffer Extension */
244CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT,
245 ENABLE_BRBE_FOR_NS)
Andre Przywarac97c5512022-11-17 16:42:09 +0000246
Andre Przywara0dda4242023-04-18 16:58:36 +0100247/* FEAT_TRBE: Trace Buffer Extension */
248CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT,
249 ENABLE_TRBE_FOR_NS)
Andre Przywarac97c5512022-11-17 16:42:09 +0000250
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000251static inline unsigned int read_feat_sme_fa64_id_field(void)
252{
Andre Przywara0dda4242023-04-18 16:58:36 +0100253 return ISOLATE_FIELD(read_id_aa64smfr0_el1(),
254 ID_AA64SMFR0_EL1_SME_FA64_SHIFT);
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000255}
Andre Przywara0dda4242023-04-18 16:58:36 +0100256/* FEAT_SMEx: Scalar Matrix Extension */
257CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
258 ENABLE_SME_FOR_NS)
259CREATE_FEATURE_FUNCS_VER(feat_sme2, read_feat_sme_id_field,
260 ID_AA64PFR1_EL1_SME2_SUPPORTED, ENABLE_SME2_FOR_NS)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +0000261
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100262/*******************************************************************************
263 * Function to get hardware granularity support
264 ******************************************************************************/
265
266static inline unsigned int read_id_aa64mmfr0_el0_tgran4_field(void)
267{
Andre Przywara0dda4242023-04-18 16:58:36 +0100268 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
269 ID_AA64MMFR0_EL1_TGRAN4_SHIFT);
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100270}
271
272static inline unsigned int read_id_aa64mmfr0_el0_tgran16_field(void)
273{
274 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
Andre Przywara0dda4242023-04-18 16:58:36 +0100275 ID_AA64MMFR0_EL1_TGRAN16_SHIFT);
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100276}
277
278static inline unsigned int read_id_aa64mmfr0_el0_tgran64_field(void)
279{
280 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
Andre Przywara0dda4242023-04-18 16:58:36 +0100281 ID_AA64MMFR0_EL1_TGRAN64_SHIFT);
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100282}
283
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000284static inline unsigned int read_feat_pmuv3_id_field(void)
285{
Andre Przywara0dda4242023-04-18 16:58:36 +0100286 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT);
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000287}
288
Boyan Karatotev677ed8a2023-02-16 09:45:29 +0000289static inline unsigned int read_feat_mtpmu_id_field(void)
290{
Andre Przywara0dda4242023-04-18 16:58:36 +0100291 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT);
Boyan Karatotev677ed8a2023-02-16 09:45:29 +0000292}
293
294static inline bool is_feat_mtpmu_supported(void)
295{
296 if (DISABLE_MTPMU == FEAT_STATE_DISABLED) {
297 return false;
298 }
299
300 if (DISABLE_MTPMU == FEAT_STATE_ALWAYS) {
301 return true;
302 }
303
304 unsigned int mtpmu = read_feat_mtpmu_id_field();
305
306 return (mtpmu != 0U) && (mtpmu != ID_AA64DFR0_MTPMU_DISABLED);
307}
308
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000309#endif /* ARCH_FEATURES_H */