blob: 1efca42a15dbc90663e4396fd77008fffa31edf7 [file] [log] [blame]
Nicolas Le Bayon8ce825f2021-05-18 10:01:30 +02001/*
2 * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
5 */
6
7#ifndef STM32MP_DDR_H
8#define STM32MP_DDR_H
9
10#include <platform_def.h>
11
12enum stm32mp_ddr_base_type {
13 DDR_BASE,
14 DDRPHY_BASE,
15 NONE_BASE
16};
17
18enum stm32mp_ddr_reg_type {
19 REG_REG,
20 REG_TIMING,
21 REG_PERF,
22 REG_MAP,
23 REGPHY_REG,
24 REGPHY_TIMING,
25 REG_TYPE_NB
26};
27
28struct stm32mp_ddr_reg_desc {
29 const char *name;
30 uint16_t offset; /* Offset for base address */
31 uint8_t par_offset; /* Offset for parameter array */
32};
33
34struct stm32mp_ddr_reg_info {
35 const char *name;
36 const struct stm32mp_ddr_reg_desc *desc;
37 uint8_t size;
38 enum stm32mp_ddr_base_type base;
39};
40
41struct stm32mp_ddr_size {
42 uint64_t base;
43 uint64_t size;
44};
45
46struct stm32mp_ddr_priv {
47 struct stm32mp_ddr_size info;
48 struct stm32mp_ddrctl *ctl;
49 struct stm32mp_ddrphy *phy;
50 uintptr_t pwr;
51 uintptr_t rcc;
52};
53
54struct stm32mp_ddr_info {
55 const char *name;
56 uint32_t speed; /* in kHZ */
57 uint32_t size; /* Memory size in byte = col * row * width */
58};
59
60#define TIMEOUT_US_1S 1000000U
61
62void stm32mp_ddr_set_reg(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_reg_type type,
63 const void *param, const struct stm32mp_ddr_reg_info *ddr_registers);
64void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl);
65void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl);
66void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl);
67int stm32mp_board_ddr_power_init(enum ddr_type ddr_type);
68
69#endif /* STM32MP_DDR_H */