| Etienne Carriere | a1249e0 | 2017-11-05 22:56:19 +0100 | [diff] [blame] | 1 | /* |
| Dimitris Papastamos | 8ca0af2 | 2018-01-03 10:48:59 +0000 | [diff] [blame^] | 2 | * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. |
| Etienne Carriere | a1249e0 | 2017-11-05 22:56:19 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <assert_macros.S> |
| 10 | #include <cortex_a9.h> |
| 11 | #include <cpu_macros.S> |
| 12 | |
| 13 | .macro assert_cache_enabled |
| 14 | #if ENABLE_ASSERTIONS |
| 15 | ldcopr r0, SCTLR |
| 16 | tst r0, #SCTLR_C_BIT |
| 17 | ASM_ASSERT(eq) |
| 18 | #endif |
| 19 | .endm |
| 20 | |
| 21 | func cortex_a9_disable_smp |
| 22 | ldcopr r0, ACTLR |
| 23 | bic r0, #CORTEX_A9_ACTLR_SMP_BIT |
| 24 | stcopr r0, ACTLR |
| 25 | isb |
| 26 | dsb sy |
| 27 | bx lr |
| 28 | endfunc cortex_a9_disable_smp |
| 29 | |
| 30 | func cortex_a9_enable_smp |
| 31 | ldcopr r0, ACTLR |
| 32 | orr r0, #CORTEX_A9_ACTLR_SMP_BIT |
| 33 | stcopr r0, ACTLR |
| 34 | isb |
| 35 | bx lr |
| 36 | endfunc cortex_a9_enable_smp |
| 37 | |
| Dimitris Papastamos | 8ca0af2 | 2018-01-03 10:48:59 +0000 | [diff] [blame^] | 38 | func check_errata_cve_2017_5715 |
| 39 | #if WORKAROUND_CVE_2017_5715 |
| 40 | mov r0, #ERRATA_APPLIES |
| 41 | #else |
| 42 | mov r0, #ERRATA_MISSING |
| 43 | #endif |
| 44 | bx lr |
| 45 | endfunc check_errata_cve_2017_5715 |
| 46 | |
| 47 | #if REPORT_ERRATA |
| 48 | /* |
| 49 | * Errata printing function for Cortex A9. Must follow AAPCS. |
| 50 | */ |
| 51 | func cortex_a9_errata_report |
| 52 | push {r12, lr} |
| 53 | |
| 54 | bl cpu_get_rev_var |
| 55 | mov r4, r0 |
| 56 | |
| 57 | /* |
| 58 | * Report all errata. The revision-variant information is passed to |
| 59 | * checking functions of each errata. |
| 60 | */ |
| 61 | report_errata WORKAROUND_CVE_2017_5715, cortex_a9, cve_2017_5715 |
| 62 | |
| 63 | pop {r12, lr} |
| 64 | bx lr |
| 65 | endfunc cortex_a9_errata_report |
| 66 | #endif |
| 67 | |
| Etienne Carriere | a1249e0 | 2017-11-05 22:56:19 +0100 | [diff] [blame] | 68 | func cortex_a9_reset_func |
| Dimitris Papastamos | 8ca0af2 | 2018-01-03 10:48:59 +0000 | [diff] [blame^] | 69 | #if IMAGE_BL32 && WORKAROUND_CVE_2017_5715 |
| 70 | ldr r0, =workaround_bpiall_runtime_exceptions |
| 71 | stcopr r0, VBAR |
| 72 | stcopr r0, MVBAR |
| 73 | /* isb will be applied in the course of the reset func */ |
| 74 | #endif |
| Etienne Carriere | a1249e0 | 2017-11-05 22:56:19 +0100 | [diff] [blame] | 75 | b cortex_a9_enable_smp |
| 76 | endfunc cortex_a9_reset_func |
| 77 | |
| 78 | func cortex_a9_core_pwr_dwn |
| 79 | push {r12, lr} |
| 80 | |
| 81 | assert_cache_enabled |
| 82 | |
| 83 | /* Flush L1 cache */ |
| 84 | mov r0, #DC_OP_CISW |
| 85 | bl dcsw_op_level1 |
| 86 | |
| 87 | /* Exit cluster coherency */ |
| 88 | pop {r12, lr} |
| 89 | b cortex_a9_disable_smp |
| 90 | endfunc cortex_a9_core_pwr_dwn |
| 91 | |
| 92 | func cortex_a9_cluster_pwr_dwn |
| 93 | push {r12, lr} |
| 94 | |
| 95 | assert_cache_enabled |
| 96 | |
| 97 | /* Flush L1 caches */ |
| 98 | mov r0, #DC_OP_CISW |
| 99 | bl dcsw_op_level1 |
| 100 | |
| 101 | bl plat_disable_acp |
| 102 | |
| 103 | /* Exit cluster coherency */ |
| 104 | pop {r12, lr} |
| 105 | b cortex_a9_disable_smp |
| 106 | endfunc cortex_a9_cluster_pwr_dwn |
| 107 | |
| 108 | declare_cpu_ops cortex_a9, CORTEX_A9_MIDR, \ |
| 109 | cortex_a9_reset_func, \ |
| 110 | cortex_a9_core_pwr_dwn, \ |
| 111 | cortex_a9_cluster_pwr_dwn |