| Etienne Carriere | 4ece755 | 2017-11-05 22:56:10 +0100 | [diff] [blame] | 1 | /* |
| Dimitris Papastamos | 8ca0af2 | 2018-01-03 10:48:59 +0000 | [diff] [blame^] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
| Etienne Carriere | 4ece755 | 2017-11-05 22:56:10 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __CORTEX_A15_H__ |
| 8 | #define __CORTEX_A15_H__ |
| 9 | |
| 10 | /******************************************************************************* |
| 11 | * Cortex-A15 midr with version/revision set to 0 |
| 12 | ******************************************************************************/ |
| 13 | #define CORTEX_A15_MIDR 0x410FC0F0 |
| 14 | |
| 15 | /******************************************************************************* |
| 16 | * CPU Auxiliary Control register specific definitions. |
| 17 | ******************************************************************************/ |
| Dimitris Papastamos | 8ca0af2 | 2018-01-03 10:48:59 +0000 | [diff] [blame^] | 18 | #define CORTEX_A15_ACTLR_INV_BTB_BIT (1 << 0) |
| Etienne Carriere | 4ece755 | 2017-11-05 22:56:10 +0100 | [diff] [blame] | 19 | #define CORTEX_A15_ACTLR_SMP_BIT (1 << 6) |
| 20 | |
| 21 | #endif /* __CORTEX_A15_H__ */ |