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Achin Gupta607084e2014-02-09 18:24:19 +00001/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta607084e2014-02-09 18:24:19 +000031#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010032#include <assert.h>
33#include <bl_common.h>
Achin Gupta607084e2014-02-09 18:24:19 +000034#include <context_mgmt.h>
Achin Gupta607084e2014-02-09 18:24:19 +000035#include <debug.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010036#include <platform.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010037#include <tsp.h>
Dan Handley714a0d22014-04-09 13:13:04 +010038#include "tspd_private.h"
Achin Gupta607084e2014-02-09 18:24:19 +000039
40/*******************************************************************************
41 * The target cpu is being turned on. Allow the TSPD/TSP to perform any actions
42 * needed. Nothing at the moment.
43 ******************************************************************************/
44static void tspd_cpu_on_handler(uint64_t target_cpu)
45{
46}
47
48/*******************************************************************************
49 * This cpu is being turned off. Allow the TSPD/TSP to perform any actions
50 * needed
51 ******************************************************************************/
52static int32_t tspd_cpu_off_handler(uint64_t cookie)
53{
54 int32_t rc = 0;
55 uint64_t mpidr = read_mpidr();
56 uint32_t linear_id = platform_get_core_pos(mpidr);
Dan Handleye2712bc2014-04-10 15:37:22 +010057 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
Achin Gupta607084e2014-02-09 18:24:19 +000058
Andrew Thoelke891c4ca2014-05-20 21:43:27 +010059 assert(tsp_vectors);
Achin Gupta18d6eaf2014-05-04 18:23:26 +010060 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON);
Achin Gupta607084e2014-02-09 18:24:19 +000061
62 /* Program the entry point and enter the TSP */
Andrew Thoelke891c4ca2014-05-20 21:43:27 +010063 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_off_entry);
Achin Gupta607084e2014-02-09 18:24:19 +000064 rc = tspd_synchronous_sp_entry(tsp_ctx);
65
66 /*
67 * Read the response from the TSP. A non-zero return means that
68 * something went wrong while communicating with the TSP.
69 */
70 if (rc != 0)
71 panic();
72
73 /*
74 * Reset TSP's context for a fresh start when this cpu is turned on
75 * subsequently.
76 */
Achin Gupta18d6eaf2014-05-04 18:23:26 +010077 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF);
Achin Gupta607084e2014-02-09 18:24:19 +000078
79 return 0;
80}
81
82/*******************************************************************************
83 * This cpu is being suspended. S-EL1 state must have been saved in the
84 * resident cpu (mpidr format) if it is a UP/UP migratable TSP.
85 ******************************************************************************/
86static void tspd_cpu_suspend_handler(uint64_t power_state)
87{
88 int32_t rc = 0;
89 uint64_t mpidr = read_mpidr();
90 uint32_t linear_id = platform_get_core_pos(mpidr);
Dan Handleye2712bc2014-04-10 15:37:22 +010091 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
Achin Gupta607084e2014-02-09 18:24:19 +000092
Andrew Thoelke891c4ca2014-05-20 21:43:27 +010093 assert(tsp_vectors);
Achin Gupta18d6eaf2014-05-04 18:23:26 +010094 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON);
Achin Gupta607084e2014-02-09 18:24:19 +000095
96 /* Program the entry point, power_state parameter and enter the TSP */
97 write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx),
98 CTX_GPREG_X0,
99 power_state);
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100100 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry);
Achin Gupta607084e2014-02-09 18:24:19 +0000101 rc = tspd_synchronous_sp_entry(tsp_ctx);
102
103 /*
104 * Read the response from the TSP. A non-zero return means that
105 * something went wrong while communicating with the TSP.
106 */
107 if (rc != 0)
108 panic();
109
110 /* Update its context to reflect the state the TSP is in */
Achin Gupta18d6eaf2014-05-04 18:23:26 +0100111 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_SUSPEND);
Achin Gupta607084e2014-02-09 18:24:19 +0000112}
113
114/*******************************************************************************
115 * This cpu has been turned on. Enter the TSP to initialise S-EL1 and other bits
116 * before passing control back to the Secure Monitor. Entry in S-El1 is done
117 * after initialising minimal architectural state that guarantees safe
118 * execution.
119 ******************************************************************************/
120static void tspd_cpu_on_finish_handler(uint64_t cookie)
121{
122 int32_t rc = 0;
123 uint64_t mpidr = read_mpidr();
124 uint32_t linear_id = platform_get_core_pos(mpidr);
Dan Handleye2712bc2014-04-10 15:37:22 +0100125 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +0100126 entry_point_info_t tsp_on_entrypoint;
Achin Gupta607084e2014-02-09 18:24:19 +0000127
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100128 assert(tsp_vectors);
Achin Gupta18d6eaf2014-05-04 18:23:26 +0100129 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_OFF);
Achin Gupta607084e2014-02-09 18:24:19 +0000130
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +0100131 tspd_init_tsp_ep_state(&tsp_on_entrypoint,
Achin Gupta607084e2014-02-09 18:24:19 +0000132 TSP_AARCH64,
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +0100133 (uint64_t) &tsp_vectors->cpu_on_entry,
Achin Gupta607084e2014-02-09 18:24:19 +0000134 tsp_ctx);
135
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +0100136 /* Initialise this cpu's secure context */
137 cm_init_context(mpidr, &tsp_on_entrypoint);
138
Achin Gupta607084e2014-02-09 18:24:19 +0000139 /* Enter the TSP */
140 rc = tspd_synchronous_sp_entry(tsp_ctx);
141
142 /*
143 * Read the response from the TSP. A non-zero return means that
144 * something went wrong while communicating with the SP.
145 */
146 if (rc != 0)
147 panic();
148
149 /* Update its context to reflect the state the SP is in */
Achin Gupta18d6eaf2014-05-04 18:23:26 +0100150 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON);
Achin Gupta607084e2014-02-09 18:24:19 +0000151}
152
153/*******************************************************************************
154 * This cpu has resumed from suspend. The SPD saved the TSP context when it
155 * completed the preceding suspend call. Use that context to program an entry
156 * into the TSP to allow it to do any remaining book keeping
157 ******************************************************************************/
158static void tspd_cpu_suspend_finish_handler(uint64_t suspend_level)
159{
160 int32_t rc = 0;
161 uint64_t mpidr = read_mpidr();
162 uint32_t linear_id = platform_get_core_pos(mpidr);
Dan Handleye2712bc2014-04-10 15:37:22 +0100163 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
Achin Gupta607084e2014-02-09 18:24:19 +0000164
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100165 assert(tsp_vectors);
Achin Gupta18d6eaf2014-05-04 18:23:26 +0100166 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_SUSPEND);
Achin Gupta607084e2014-02-09 18:24:19 +0000167
168 /* Program the entry point, suspend_level and enter the SP */
169 write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx),
170 CTX_GPREG_X0,
171 suspend_level);
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100172 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry);
Achin Gupta607084e2014-02-09 18:24:19 +0000173 rc = tspd_synchronous_sp_entry(tsp_ctx);
174
175 /*
176 * Read the response from the TSP. A non-zero return means that
177 * something went wrong while communicating with the TSP.
178 */
179 if (rc != 0)
180 panic();
181
182 /* Update its context to reflect the state the SP is in */
Achin Gupta18d6eaf2014-05-04 18:23:26 +0100183 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON);
Achin Gupta607084e2014-02-09 18:24:19 +0000184}
185
186/*******************************************************************************
187 * Return the type of TSP the TSPD is dealing with. Report the current resident
188 * cpu (mpidr format) if it is a UP/UP migratable TSP.
189 ******************************************************************************/
190static int32_t tspd_cpu_migrate_info(uint64_t *resident_cpu)
191{
192 return TSP_MIGRATE_INFO;
193}
194
195/*******************************************************************************
Juan Castillo4dc4a472014-08-12 11:17:06 +0100196 * System is about to be switched off. Allow the TSPD/TSP to perform
197 * any actions needed.
198 ******************************************************************************/
199static void tspd_system_off(void)
200{
201 uint64_t mpidr = read_mpidr();
202 uint32_t linear_id = platform_get_core_pos(mpidr);
203 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
204
205 assert(tsp_vectors);
206 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON);
207
208 /* Program the entry point */
209 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_off_entry);
210
211 /* Enter the TSP. We do not care about the return value because we
212 * must continue the shutdown anyway */
213 tspd_synchronous_sp_entry(tsp_ctx);
214}
215
216/*******************************************************************************
217 * System is about to be reset. Allow the TSPD/TSP to perform
218 * any actions needed.
219 ******************************************************************************/
220static void tspd_system_reset(void)
221{
222 uint64_t mpidr = read_mpidr();
223 uint32_t linear_id = platform_get_core_pos(mpidr);
224 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
225
226 assert(tsp_vectors);
227 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON);
228
229 /* Program the entry point */
230 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_reset_entry);
231
232 /* Enter the TSP. We do not care about the return value because we
233 * must continue the reset anyway */
234 tspd_synchronous_sp_entry(tsp_ctx);
235}
236
237/*******************************************************************************
Achin Gupta607084e2014-02-09 18:24:19 +0000238 * Structure populated by the TSP Dispatcher to be given a chance to perform any
239 * TSP bookkeeping before PSCI executes a power mgmt. operation.
240 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100241const spd_pm_ops_t tspd_pm = {
Juan Castillo4dc4a472014-08-12 11:17:06 +0100242 .svc_on = tspd_cpu_on_handler,
243 .svc_off = tspd_cpu_off_handler,
244 .svc_suspend = tspd_cpu_suspend_handler,
245 .svc_on_finish = tspd_cpu_on_finish_handler,
246 .svc_suspend_finish = tspd_cpu_suspend_finish_handler,
247 .svc_migrate = NULL,
248 .svc_migrate_info = tspd_cpu_migrate_info,
249 .svc_system_off = tspd_system_off,
250 .svc_system_reset = tspd_system_reset
Achin Gupta607084e2014-02-09 18:24:19 +0000251};