blob: dfe1dcfb33a132e4ece907d9323b774ce1f8af57 [file] [log] [blame]
Chungying Lua566cc92023-03-15 14:16:28 +08001/*
2 * Copyright (c) 2023, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/* TF-A system header */
8#include <common/debug.h>
9
10/* Vendor header */
11#include "apusys.h"
Karl Li130536e2023-04-21 11:43:24 +080012#include "apusys_devapc.h"
Chungying Lua566cc92023-03-15 14:16:28 +080013#include "apusys_power.h"
Karl Lieb629492023-04-27 14:00:10 +080014#include "apusys_rv.h"
Karl Lidece5f02023-04-27 10:38:28 +080015#include "apusys_security_ctrl_plat.h"
Chungying Lua566cc92023-03-15 14:16:28 +080016#include <lib/mtk_init/mtk_init.h>
Chungying Luf1f14b32023-03-15 15:31:56 +080017#include <mtk_sip_svc.h>
18
19static u_register_t apusys_kernel_handler(u_register_t x1,
20 u_register_t x2,
21 u_register_t x3,
22 u_register_t x4,
23 void *handle,
24 struct smccc_res *smccc_ret)
25{
26 uint32_t request_ops;
27 int32_t ret = -1;
28
29 request_ops = (uint32_t)x1;
30
31 switch (request_ops) {
32 case MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_ON:
33 ret = apusys_kernel_apusys_pwr_top_on();
34 break;
35 case MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_OFF:
36 ret = apusys_kernel_apusys_pwr_top_off();
37 break;
Chungying Lu15ffb072023-04-19 17:17:23 +080038 case MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_REVISER:
39 ret = apusys_kernel_apusys_rv_setup_reviser();
40 break;
41 case MTK_APUSYS_KERNEL_OP_APUSYS_RV_RESET_MP:
42 ret = apusys_kernel_apusys_rv_reset_mp();
43 break;
44 case MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_BOOT:
45 ret = apusys_kernel_apusys_rv_setup_boot();
46 break;
47 case MTK_APUSYS_KERNEL_OP_APUSYS_RV_START_MP:
48 ret = apusys_kernel_apusys_rv_start_mp();
49 break;
50 case MTK_APUSYS_KERNEL_OP_APUSYS_RV_STOP_MP:
51 ret = apusys_kernel_apusys_rv_stop_mp();
52 break;
Karl Li03facb02023-04-24 16:45:49 +080053 case MTK_APUSYS_KERNEL_OP_DEVAPC_INIT_RCX:
54 ret = apusys_devapc_rcx_init();
55 break;
Chungying Lu59c1c2b2023-04-25 15:39:10 +080056 case MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_SEC_MEM:
57 ret = apusys_kernel_apusys_rv_setup_sec_mem();
58 break;
Chungying Lu4f3b5da2023-05-12 18:37:32 +080059 case MTK_APUSYS_KERNEL_OP_APUSYS_RV_DISABLE_WDT_ISR:
60 ret = apusys_kernel_apusys_rv_disable_wdt_isr();
61 break;
62 case MTK_APUSYS_KERNEL_OP_APUSYS_RV_CLEAR_WDT_ISR:
63 ret = apusys_kernel_apusys_rv_clear_wdt_isr();
64 break;
65 case MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_GATING:
66 ret = apusys_kernel_apusys_rv_cg_gating();
67 break;
68 case MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_UNGATING:
69 ret = apusys_kernel_apusys_rv_cg_ungating();
70 break;
Chungying Luf1f14b32023-03-15 15:31:56 +080071 default:
72 ERROR(MODULE_TAG "%s unknown request_ops = %x\n", MODULE_TAG, request_ops);
73 break;
74 }
75
76 return ret;
77}
78DECLARE_SMC_HANDLER(MTK_SIP_APUSYS_CONTROL, apusys_kernel_handler);
Chungying Lua566cc92023-03-15 14:16:28 +080079
80int apusys_init(void)
81{
Karl Li130536e2023-04-21 11:43:24 +080082 if (apusys_power_init() != 0) {
83 return -1;
84 }
85
86 if (apusys_devapc_ao_init() != 0) {
87 return -1;
88 }
89
Karl Lidece5f02023-04-27 10:38:28 +080090 apusys_security_ctrl_init();
Karl Lieb629492023-04-27 14:00:10 +080091 apusys_rv_mbox_mpu_init();
Karl Lidece5f02023-04-27 10:38:28 +080092
Chungying Lua566cc92023-03-15 14:16:28 +080093 return 0;
94}
95MTK_PLAT_SETUP_1_INIT(apusys_init);