blob: 91d33705d7d9ac3ab4264b5f510b479322ccd9af [file] [log] [blame]
Anson Huangd2b90552018-07-12 10:52:55 +08001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <stdbool.h>
8
Anson Huangd2b90552018-07-12 10:52:55 +08009#include <arch.h>
10#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/debug.h>
12
Anson Huangd2b90552018-07-12 10:52:55 +080013#include <plat_imx8.h>
14#include <sci/sci.h>
Anson Huangd2b90552018-07-12 10:52:55 +080015
16void __dead2 imx_system_off(void)
17{
18 sc_pm_set_sys_power_mode(ipc_handle, SC_PM_PW_MODE_OFF);
19 wfi();
20 ERROR("power off failed.\n");
21 panic();
22}
23
Anson Huang0da07d22018-07-12 11:04:15 +080024void __dead2 imx_system_reset(void)
25{
26 sc_pm_reset(ipc_handle, SC_PM_RESET_TYPE_BOARD);
27 wfi();
28 ERROR("system reset failed.\n");
29 panic();
30}
Anson Huangd2b90552018-07-12 10:52:55 +080031
Anson Huang10cd8172018-07-12 14:17:19 +080032int imx_validate_power_state(unsigned int power_state,
33 psci_power_state_t *req_state)
34{
Anson Huangad192dc2019-01-24 16:09:52 +080035 int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
36 int pwr_type = psci_get_pstate_type(power_state);
37 int state_id = psci_get_pstate_id(power_state);
38
39 if (pwr_lvl > PLAT_MAX_PWR_LVL)
40 return PSCI_E_INVALID_PARAMS;
41
42 if (pwr_type == PSTATE_TYPE_POWERDOWN) {
43 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
44 if (!state_id)
45 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_RET_STATE;
46 else
47 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_OFF_STATE;
48 }
49
50 return PSCI_E_SUCCESS;
Anson Huang10cd8172018-07-12 14:17:19 +080051}
52
53void imx_get_sys_suspend_power_state(psci_power_state_t *req_state)
54{
55 unsigned int i;
56
57 /* CPU & cluster off, system in retention */
58 for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
59 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
60 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE;
61}
62