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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta8aa0cd42014-02-09 13:47:08 +000031#include <stdio.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <console.h>
33#include <platform.h>
34#include <pl011.h>
35
Achin Gupta8aa0cd42014-02-09 13:47:08 +000036static unsigned long uart_base = PL011_BASE;
37
Achin Gupta4f6ad662013-10-25 09:08:21 +010038/*
39 * TODO: Console init functions shoule be in a console.c. This file should
40 * only contain the pl011 accessors.
41 */
Achin Gupta8aa0cd42014-02-09 13:47:08 +000042void console_init(unsigned long base_addr)
Achin Gupta4f6ad662013-10-25 09:08:21 +010043{
44 unsigned int divisor;
45
Achin Gupta8aa0cd42014-02-09 13:47:08 +000046 /* Initialise internal base address variable */
47 uart_base = base_addr;
48
Achin Gupta4f6ad662013-10-25 09:08:21 +010049 /* Baud Rate */
50
51#if defined(PL011_INTEGER) && defined(PL011_FRACTIONAL)
Achin Gupta8aa0cd42014-02-09 13:47:08 +000052 mmio_write_32(uart_base + UARTIBRD, PL011_INTEGER);
53 mmio_write_32(uart_base + UARTFBRD, PL011_FRACTIONAL);
Achin Gupta4f6ad662013-10-25 09:08:21 +010054#else
55 divisor = (PL011_CLK_IN_HZ * 4) / PL011_BAUDRATE;
Achin Gupta8aa0cd42014-02-09 13:47:08 +000056 mmio_write_32(uart_base + UARTIBRD, divisor >> 6);
57 mmio_write_32(uart_base + UARTFBRD, divisor & 0x3F);
Achin Gupta4f6ad662013-10-25 09:08:21 +010058#endif
59
60
Achin Gupta8aa0cd42014-02-09 13:47:08 +000061 mmio_write_32(uart_base + UARTLCR_H, PL011_LINE_CONTROL);
Achin Gupta4f6ad662013-10-25 09:08:21 +010062
63 /* Clear any pending errors */
Achin Gupta8aa0cd42014-02-09 13:47:08 +000064 mmio_write_32(uart_base + UARTECR, 0);
Achin Gupta4f6ad662013-10-25 09:08:21 +010065
66 /* Enable tx, rx, and uart overall */
Achin Gupta8aa0cd42014-02-09 13:47:08 +000067 mmio_write_32(uart_base + UARTCR,
Achin Gupta4f6ad662013-10-25 09:08:21 +010068 PL011_UARTCR_RXE | PL011_UARTCR_TXE |
69 PL011_UARTCR_UARTEN);
70}
71
72int console_putc(int c)
73{
74 if (c == '\n') {
75 console_putc('\r');
76 }
Achin Gupta8aa0cd42014-02-09 13:47:08 +000077
78 while ((mmio_read_32(uart_base + UARTFR) & PL011_UARTFR_TXFE) == 0)
79 ;
80 mmio_write_32(uart_base + UARTDR, c);
Achin Gupta4f6ad662013-10-25 09:08:21 +010081 return c;
82}
83
84int console_getc(void)
85{
Achin Gupta8aa0cd42014-02-09 13:47:08 +000086 while ((mmio_read_32(uart_base + UARTFR) & PL011_UARTFR_RXFE) != 0)
87 ;
88 return mmio_read_32(uart_base + UARTDR);
Achin Gupta4f6ad662013-10-25 09:08:21 +010089}