developer | 451d49d | 2022-11-16 21:52:21 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2023, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef MT_SPM_COND_H |
| 8 | #define MT_SPM_COND_H |
| 9 | |
| 10 | #include <lpm/mt_lp_rm.h> |
| 11 | |
| 12 | enum plat_spm_cond { |
| 13 | PLAT_SPM_COND_MTCMOS1 = 0, |
| 14 | PLAT_SPM_COND_MTCMOS2, |
| 15 | PLAT_SPM_COND_CG_INFRA_0, |
| 16 | PLAT_SPM_COND_CG_INFRA_1, |
| 17 | PLAT_SPM_COND_CG_INFRA_2, |
| 18 | PLAT_SPM_COND_CG_INFRA_3, |
| 19 | PLAT_SPM_COND_CG_INFRA_4, |
| 20 | PLAT_SPM_COND_CG_PERI_0, |
| 21 | PLAT_SPM_COND_CG_VPPSYS0_0, |
| 22 | PLAT_SPM_COND_CG_VPPSYS0_1, |
| 23 | PLAT_SPM_COND_CG_VPPSYS1_0, |
| 24 | PLAT_SPM_COND_CG_VPPSYS1_1, |
| 25 | PLAT_SPM_COND_CG_VDOSYS0_0, |
| 26 | PLAT_SPM_COND_CG_VDOSYS0_1, |
| 27 | PLAT_SPM_COND_CG_VDOSYS1_0, |
| 28 | PLAT_SPM_COND_CG_VDOSYS1_1, |
| 29 | PLAT_SPM_COND_CG_VDOSYS1_2, |
| 30 | PLAT_SPM_COND_MAX, |
| 31 | }; |
| 32 | |
| 33 | /* For PLL id >= PLAT_SPM_COND_PLL_MAX is not checked in idle condition */ |
| 34 | enum plat_spm_cond_pll { |
| 35 | PLAT_SPM_COND_PLL_UNIVPLL = 0, |
| 36 | PLAT_SPM_COND_PLL_MFGPLL, |
| 37 | PLAT_SPM_COND_PLL_MSDCPLL, |
| 38 | PLAT_SPM_COND_PLL_TVDPLL1, |
| 39 | PLAT_SPM_COND_PLL_TVDPLL2, |
| 40 | PLAT_SPM_COND_PLL_MMPLL, |
| 41 | PLAT_SPM_COND_PLL_ETHPLL, |
| 42 | PLAT_SPM_COND_PLL_IMGPLL, |
| 43 | PLAT_SPM_COND_PLL_APLL1, |
| 44 | PLAT_SPM_COND_PLL_APLL2, |
| 45 | PLAT_SPM_COND_PLL_APLL3, |
| 46 | PLAT_SPM_COND_PLL_APLL4, |
| 47 | PLAT_SPM_COND_PLL_APLL5, |
| 48 | PLAT_SPM_COND_PLL_MAX, |
| 49 | }; |
| 50 | |
| 51 | #define PLL_BIT_MFGPLL BIT(PLAT_SPM_COND_PLL_MFGPLL) |
| 52 | #define PLL_BIT_MMPLL BIT(PLAT_SPM_COND_PLL_MMPLL) |
| 53 | #define PLL_BIT_UNIVPLL BIT(PLAT_SPM_COND_PLL_UNIVPLL) |
| 54 | #define PLL_BIT_MSDCPLL BIT(PLAT_SPM_COND_PLL_MSDCPLL) |
| 55 | #define PLL_BIT_TVDPLL1 BIT(PLAT_SPM_COND_PLL_TVDPLL1) |
| 56 | #define PLL_BIT_TVDPLL2 BIT(PLAT_SPM_COND_PLL_TVDPLL2) |
| 57 | #define PLL_BIT_ETHPLL BIT(PLAT_SPM_COND_PLL_ETHPLL) |
| 58 | #define PLL_BIT_IMGPLL BIT(PLAT_SPM_COND_PLL_IMGPLL) |
| 59 | #define PLL_BIT_APLL1 BIT(PLAT_SPM_COND_PLL_APLL1) |
| 60 | #define PLL_BIT_APLL2 BIT(PLAT_SPM_COND_PLL_APLL2) |
| 61 | #define PLL_BIT_APLL3 BIT(PLAT_SPM_COND_PLL_APLL3) |
| 62 | #define PLL_BIT_APLL4 BIT(PLAT_SPM_COND_PLL_APLL4) |
| 63 | #define PLL_BIT_APLL5 BIT(PLAT_SPM_COND_PLL_APLL5) |
| 64 | |
| 65 | /* |
| 66 | * Definition about SPM_COND_CHECK_BLOCKED |
| 67 | * bit[00:16]: cg blocking index |
| 68 | * bit[17:29]: pll blocking index |
| 69 | * bit[30]: pll blocking information |
| 70 | * bit[31]: idle condition check fail |
| 71 | */ |
| 72 | #define SPM_COND_BLOCKED_CG_IDX (0) |
| 73 | #define SPM_COND_BLOCKED_PLL_IDX (17) |
| 74 | #define SPM_COND_CHECK_BLOCKED_PLL BIT(30) |
| 75 | #define SPM_COND_CHECK_FAIL BIT(31) |
| 76 | |
| 77 | struct mt_spm_cond_tables { |
| 78 | unsigned int table_cg[PLAT_SPM_COND_MAX]; |
| 79 | unsigned int table_pll; |
| 80 | unsigned int table_all_pll; |
| 81 | void *priv; |
| 82 | }; |
| 83 | |
| 84 | unsigned int mt_spm_cond_check(const struct mt_spm_cond_tables *src, |
| 85 | const struct mt_spm_cond_tables *dest, |
| 86 | struct mt_spm_cond_tables *res); |
| 87 | unsigned int mt_spm_dump_all_pll(const struct mt_spm_cond_tables *src, |
| 88 | const struct mt_spm_cond_tables *dest, |
| 89 | struct mt_spm_cond_tables *res); |
developer | fbc1ea9 | 2023-01-06 15:50:33 +0800 | [diff] [blame] | 90 | int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num, |
| 91 | int stateid, void *priv); |
developer | 451d49d | 2022-11-16 21:52:21 +0800 | [diff] [blame] | 92 | |
| 93 | #endif |