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Jens Wiklander52c798e2015-12-07 14:37:10 +01001/*
2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30#include <arch_helpers.h>
31#include <bl_common.h>
32#include <console.h>
33#include <debug.h>
34#include <libfdt.h>
35#include <platform_def.h>
36#include "qemu_private.h"
37#include <string.h>
38
39
40/*
41 * The next 2 constants identify the extents of the code & RO data region.
42 * These addresses are used by the MMU setup code and therefore they must be
43 * page-aligned. It is the responsibility of the linker script to ensure that
44 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
45 */
46#define BL2_RO_BASE (unsigned long)(&__RO_START__)
47#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
48
Jens Wiklander52c798e2015-12-07 14:37:10 +010049/*******************************************************************************
50 * This structure represents the superset of information that is passed to
51 * BL3-1, e.g. while passing control to it from BL2, bl31_params
52 * and other platform specific params
53 ******************************************************************************/
54typedef struct bl2_to_bl31_params_mem {
55 bl31_params_t bl31_params;
56 image_info_t bl31_image_info;
57 image_info_t bl32_image_info;
58 image_info_t bl33_image_info;
59 entry_point_info_t bl33_ep_info;
60 entry_point_info_t bl32_ep_info;
61 entry_point_info_t bl31_ep_info;
62} bl2_to_bl31_params_mem_t;
63
64
65static bl2_to_bl31_params_mem_t bl31_params_mem;
66
67
68
69/* Data structure which holds the extents of the trusted SRAM for BL2 */
70static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
71
72meminfo_t *bl2_plat_sec_mem_layout(void)
73{
74 return &bl2_tzram_layout;
75}
76
77/*******************************************************************************
78 * This function assigns a pointer to the memory that the platform has kept
79 * aside to pass platform specific and trusted firmware related information
80 * to BL31. This memory is allocated by allocating memory to
81 * bl2_to_bl31_params_mem_t structure which is a superset of all the
82 * structure whose information is passed to BL31
83 * NOTE: This function should be called only once and should be done
84 * before generating params to BL31
85 ******************************************************************************/
86bl31_params_t *bl2_plat_get_bl31_params(void)
87{
88 bl31_params_t *bl2_to_bl31_params;
89
90 /*
91 * Initialise the memory for all the arguments that needs to
92 * be passed to BL3-1
93 */
94 memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t));
95
96 /* Assign memory for TF related information */
97 bl2_to_bl31_params = &bl31_params_mem.bl31_params;
98 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
99
100 /* Fill BL3-1 related information */
101 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
102 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
103 VERSION_1, 0);
104
105 /* Fill BL3-2 related information */
106 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
107 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
108 VERSION_1, 0);
109 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
110 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
111 VERSION_1, 0);
112
113 /* Fill BL3-3 related information */
114 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
115 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
116 PARAM_EP, VERSION_1, 0);
117
118 /* BL3-3 expects to receive the primary CPU MPID (through x0) */
119 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
120
121 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
122 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
123 VERSION_1, 0);
124
125 return bl2_to_bl31_params;
126}
127
128/* Flush the TF params and the TF plat params */
129void bl2_plat_flush_bl31_params(void)
130{
131 flush_dcache_range((unsigned long)&bl31_params_mem,
132 sizeof(bl2_to_bl31_params_mem_t));
133}
134
135/*******************************************************************************
136 * This function returns a pointer to the shared memory that the platform
137 * has kept to point to entry point information of BL31 to BL2
138 ******************************************************************************/
139struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
140{
141#if DEBUG
142 bl31_params_mem.bl31_ep_info.args.arg1 = QEMU_BL31_PLAT_PARAM_VAL;
143#endif
144
145 return &bl31_params_mem.bl31_ep_info;
146}
147
148
149
150void bl2_early_platform_setup(meminfo_t *mem_layout)
151{
152 /* Initialize the console to provide early debug support */
153 console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ,
154 PLAT_QEMU_CONSOLE_BAUDRATE);
155
156 /* Setup the BL2 memory layout */
157 bl2_tzram_layout = *mem_layout;
158
159 plat_qemu_io_setup();
160}
161
162static void security_setup(void)
163{
164 /*
165 * This is where a TrustZone address space controller and other
166 * security related peripherals, would be configured.
167 */
168}
169
170static void update_dt(void)
171{
172 int ret;
173 void *fdt = (void *)(uintptr_t)PLAT_QEMU_DT_BASE;
174
175 ret = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE);
176 if (ret < 0) {
177 ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret);
178 return;
179 }
180
181 if (dt_add_psci_node(fdt)) {
182 ERROR("Failed to add PSCI Device Tree node\n");
183 return;
184 }
185
186 if (dt_add_psci_cpu_enable_methods(fdt)) {
187 ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
188 return;
189 }
190
191 ret = fdt_pack(fdt);
192 if (ret < 0)
193 ERROR("Failed to pack Device Tree at %p: error %d\n", fdt, ret);
194}
195
196void bl2_platform_setup(void)
197{
198 security_setup();
199 update_dt();
200
201 /* TODO Initialize timer */
202}
203
204void bl2_plat_arch_setup(void)
205{
206 qemu_configure_mmu_el1(bl2_tzram_layout.total_base,
207 bl2_tzram_layout.total_size,
208 BL2_RO_BASE, BL2_RO_LIMIT,
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900209 BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
Jens Wiklander52c798e2015-12-07 14:37:10 +0100210}
211
212/*******************************************************************************
213 * Gets SPSR for BL32 entry
214 ******************************************************************************/
215static uint32_t qemu_get_spsr_for_bl32_entry(void)
216{
217 /*
218 * The Secure Payload Dispatcher service is responsible for
219 * setting the SPSR prior to entry into the BL3-2 image.
220 */
221 return 0;
222}
223
224/*******************************************************************************
225 * Gets SPSR for BL33 entry
226 ******************************************************************************/
227static uint32_t qemu_get_spsr_for_bl33_entry(void)
228{
229 unsigned long el_status;
230 unsigned int mode;
231 uint32_t spsr;
232
233 /* Figure out what mode we enter the non-secure world in */
234 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
235 el_status &= ID_AA64PFR0_ELX_MASK;
236
237 mode = (el_status) ? MODE_EL2 : MODE_EL1;
238
239 /*
240 * TODO: Consider the possibility of specifying the SPSR in
241 * the FIP ToC and allowing the platform to have a say as
242 * well.
243 */
244 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
245 return spsr;
246}
247
248/*******************************************************************************
249 * Before calling this function BL3-1 is loaded in memory and its entrypoint
250 * is set by load_image. This is a placeholder for the platform to change
251 * the entrypoint of BL3-1 and set SPSR and security state.
252 * On ARM standard platforms we only set the security state of the entrypoint
253 ******************************************************************************/
254void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
255 entry_point_info_t *bl31_ep_info)
256{
257 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
258 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
259 DISABLE_ALL_EXCEPTIONS);
260}
261
262/*******************************************************************************
263 * Before calling this function BL3-2 is loaded in memory and its entrypoint
264 * is set by load_image. This is a placeholder for the platform to change
265 * the entrypoint of BL3-2 and set SPSR and security state.
266 * On ARM standard platforms we only set the security state of the entrypoint
267 ******************************************************************************/
268void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
269 entry_point_info_t *bl32_ep_info)
270{
271 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
272 bl32_ep_info->spsr = qemu_get_spsr_for_bl32_entry();
273}
274
275/*******************************************************************************
276 * Before calling this function BL3-3 is loaded in memory and its entrypoint
277 * is set by load_image. This is a placeholder for the platform to change
278 * the entrypoint of BL3-3 and set SPSR and security state.
279 * On ARM standard platforms we only set the security state of the entrypoint
280 ******************************************************************************/
281void bl2_plat_set_bl33_ep_info(image_info_t *image,
282 entry_point_info_t *bl33_ep_info)
283{
284
285 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
286 bl33_ep_info->spsr = qemu_get_spsr_for_bl33_entry();
287}
288
289/*******************************************************************************
290 * Populate the extents of memory available for loading BL32
291 ******************************************************************************/
292void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
293{
294 /*
295 * Populate the extents of memory available for loading BL32.
296 */
297 bl32_meminfo->total_base = BL32_BASE;
298 bl32_meminfo->free_base = BL32_BASE;
299 bl32_meminfo->total_size = (BL32_MEM_BASE + BL32_MEM_SIZE) - BL32_BASE;
300 bl32_meminfo->free_size = (BL32_MEM_BASE + BL32_MEM_SIZE) - BL32_BASE;
301}
302
303/*******************************************************************************
304 * Populate the extents of memory available for loading BL33
305 ******************************************************************************/
306void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
307{
308 bl33_meminfo->total_base = NS_DRAM0_BASE;
309 bl33_meminfo->total_size = NS_DRAM0_SIZE;
310 bl33_meminfo->free_base = NS_DRAM0_BASE;
311 bl33_meminfo->free_size = NS_DRAM0_SIZE;
312}
313
314unsigned long plat_get_ns_image_entrypoint(void)
315{
316 return NS_IMAGE_OFFSET;
317}