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Jens Wiklander52c798e2015-12-07 14:37:10 +01001/*
2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __PLATFORM_DEF_H__
32#define __PLATFORM_DEF_H__
33
34#include <arch.h>
35#include <common_def.h>
36#include <tbbr_img_def.h>
37
38/* Special value used to verify platform parameters from BL2 to BL3-1 */
39#define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
40
41#define PLATFORM_STACK_SIZE 0x1000
42
43#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
44#define PLATFORM_CLUSTER_COUNT 2
45#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
46#define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
47#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
48 PLATFORM_CLUSTER1_CORE_COUNT)
49
50#define QEMU_PRIMARY_CPU 0
51
52#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
53 PLATFORM_CORE_COUNT)
54#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
55
56#define PLAT_MAX_RET_STATE 1
57#define PLAT_MAX_OFF_STATE 2
58
59/* Local power state for power domains in Run state. */
60#define PLAT_LOCAL_STATE_RUN 0
61/* Local power state for retention. Valid only for CPU power domains */
62#define PLAT_LOCAL_STATE_RET 1
63/*
64 * Local power state for OFF/power-down. Valid for CPU and cluster power
65 * domains.
66 */
67#define PLAT_LOCAL_STATE_OFF 2
68
69/*
70 * Macros used to parse state information from State-ID if it is using the
71 * recommended encoding for State-ID.
72 */
73#define PLAT_LOCAL_PSTATE_WIDTH 4
74#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
75
76/*
77 * Some data must be aligned on the biggest cache line size in the platform.
78 * This is known only to the platform as it might have a combination of
79 * integrated and external caches.
80 */
81#define CACHE_WRITEBACK_SHIFT 6
82#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
83
84/*
85 * Partition memory into secure ROM, non-secure DRAM, secure "SRAM",
86 * and secure DRAM.
87 */
88#define SEC_ROM_BASE 0x00000000
89#define SEC_ROM_SIZE 0x00020000
90
91#define NS_DRAM0_BASE 0x40000000
92#define NS_DRAM0_SIZE 0x3de00000
93
94#define SEC_SRAM_BASE 0x0e000000
95#define SEC_SRAM_SIZE 0x00040000
96
97#define SEC_DRAM_BASE 0x0e100000
98#define SEC_DRAM_SIZE 0x00f00000
99
100/*
101 * ARM-TF lives in SRAM, partition it here
102 */
103
104#define SHARED_RAM_BASE SEC_SRAM_BASE
105#define SHARED_RAM_SIZE 0x00001000
106
107#define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE
108#define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE)
109#define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8)
110#define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \
111 PLAT_QEMU_HOLD_ENTRY_SIZE)
112#define PLAT_QEMU_HOLD_ENTRY_SIZE 8
113#define PLAT_QEMU_HOLD_STATE_WAIT 0
114#define PLAT_QEMU_HOLD_STATE_GO 1
115
116#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE)
117#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
118
119/*
120 * BL1 specific defines.
121 *
122 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
123 * addresses.
124 * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using
125 * the current BL1 RW debug size plus a little space for growth.
126 */
127#define BL1_RO_BASE SEC_ROM_BASE
128#define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE)
129#define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000)
130#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
131
132/*
133 * BL2 specific defines.
134 *
135 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
136 * size plus a little space for growth.
137 */
138#define BL2_BASE (BL31_BASE - 0x1D000)
139#define BL2_LIMIT BL31_BASE
140
141/*
142 * BL3-1 specific defines.
143 *
144 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
145 * current BL3-1 debug size plus a little space for growth.
146 */
147#define BL31_BASE (BL31_LIMIT - 0x20000)
148#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
149#define BL31_PROGBITS_LIMIT BL1_RW_BASE
150
151
152/*
153 * BL3-2 specific defines.
154 *
155 * BL3-2 can execute from Secure SRAM, or Secure DRAM.
156 */
157#define BL32_SRAM_BASE BL_RAM_BASE
158#define BL32_SRAM_LIMIT BL31_BASE
159#define BL32_DRAM_BASE SEC_DRAM_BASE
160#define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE)
161
162#define SEC_SRAM_ID 0
163#define SEC_DRAM_ID 1
164
165#if BL32_RAM_LOCATION_ID == SEC_SRAM_ID
166# define BL32_MEM_BASE BL_RAM_BASE
167# define BL32_MEM_SIZE BL_RAM_SIZE
168# define BL32_BASE BL32_SRAM_BASE
169# define BL32_LIMIT BL32_SRAM_LIMIT
170#elif BL32_RAM_LOCATION_ID == SEC_DRAM_ID
171# define BL32_MEM_BASE SEC_DRAM_BASE
172# define BL32_MEM_SIZE SEC_DRAM_SIZE
173# define BL32_BASE BL32_DRAM_BASE
174# define BL32_LIMIT BL32_DRAM_LIMIT
175#else
176# error "Unsupported BL32_RAM_LOCATION_ID value"
177#endif
Jens Wiklander52c798e2015-12-07 14:37:10 +0100178
179#define NS_IMAGE_OFFSET 0x60000000
180
181#define ADDR_SPACE_SIZE (1ull << 32)
182#define MAX_MMAP_REGIONS 8
183#define MAX_XLAT_TABLES 6
184#define MAX_IO_DEVICES 3
185#define MAX_IO_HANDLES 4
186
187/*
188 * PL011 related constants
189 */
190#define UART0_BASE 0x09000000
191#define UART1_BASE 0x09040000
192#define UART0_CLK_IN_HZ 1
193#define UART1_CLK_IN_HZ 1
194
195#define PLAT_QEMU_BOOT_UART_BASE UART0_BASE
196#define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ
197
198#define PLAT_QEMU_CRASH_UART_BASE UART1_BASE
199#define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ
200
201#define PLAT_QEMU_CONSOLE_BAUDRATE 115200
202
203#define QEMU_FLASH0_BASE 0x04000000
204#define QEMU_FLASH0_SIZE 0x04000000
205
206#define PLAT_QEMU_FIP_BASE QEMU_FLASH0_BASE
207#define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH0_SIZE
208
209#define DEVICE0_BASE 0x08000000
210#define DEVICE0_SIZE 0x00021000
211#define DEVICE1_BASE 0x09000000
212#define DEVICE1_SIZE 0x00011000
213
214/*
215 * GIC related constants
216 */
217
218#define GICD_BASE 0x8000000
219#define GICC_BASE 0x8010000
220#define GICR_BASE 0
221
222
223#define QEMU_IRQ_SEC_SGI_0 8
224#define QEMU_IRQ_SEC_SGI_1 9
225#define QEMU_IRQ_SEC_SGI_2 10
226#define QEMU_IRQ_SEC_SGI_3 11
227#define QEMU_IRQ_SEC_SGI_4 12
228#define QEMU_IRQ_SEC_SGI_5 13
229#define QEMU_IRQ_SEC_SGI_6 14
230#define QEMU_IRQ_SEC_SGI_7 15
231
232/*
233 * DT related constants
234 */
235#define PLAT_QEMU_DT_BASE NS_DRAM0_BASE
236#define PLAT_QEMU_DT_MAX_SIZE 0x10000
237
238/*
239 * System counter
240 */
241#define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16)
242
243#endif /* __PLATFORM_DEF_H__ */