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Marcin Juszkiewicz7754e822023-07-24 20:56:29 +02001#
Jean-Philippe Brucker6125ee42023-09-06 16:18:02 +01002# Copyright (c) 2023-2024, Linaro Limited and Contributors. All rights reserved.
Marcin Juszkiewicz7754e822023-07-24 20:56:29 +02003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include lib/libfdt/libfdt.mk
8include common/fdt_wrappers.mk
9
Marcin Juszkiewicza70ef5e2023-07-24 21:08:16 +020010PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
11 -I${PLAT_QEMU_COMMON_PATH}/include \
12 -I${PLAT_QEMU_PATH}/include \
13 -Iinclude/common/tbbr
14
15ifeq (${ARCH},aarch32)
16QEMU_CPU_LIBS := lib/cpus/${ARCH}/cortex_a15.S
17else
18QEMU_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \
19 lib/cpus/aarch64/cortex_a53.S \
developer618fd512023-09-13 19:50:24 +080020 lib/cpus/aarch64/cortex_a55.S \
Marcin Juszkiewicza70ef5e2023-07-24 21:08:16 +020021 lib/cpus/aarch64/cortex_a57.S \
22 lib/cpus/aarch64/cortex_a72.S \
23 lib/cpus/aarch64/cortex_a76.S \
Marcin Juszkiewicz4b5a2c22023-09-12 13:08:13 +020024 lib/cpus/aarch64/cortex_a710.S \
Marcin Juszkiewicza70ef5e2023-07-24 21:08:16 +020025 lib/cpus/aarch64/neoverse_n_common.S \
26 lib/cpus/aarch64/neoverse_n1.S \
27 lib/cpus/aarch64/neoverse_v1.S \
Marcin Juszkiewiczc36f42b2023-09-15 22:44:04 +020028 lib/cpus/aarch64/neoverse_n2.S \
Marcin Juszkiewicza70ef5e2023-07-24 21:08:16 +020029 lib/cpus/aarch64/qemu_max.S
30
31PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
32endif
Marcin Juszkiewicz424e3a82023-07-24 21:18:51 +020033
34PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
35 ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \
36 drivers/arm/pl011/${ARCH}/pl011_console.S
37
38include lib/xlat_tables_v2/xlat_tables.mk
39PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
40
41ifneq ($(ENABLE_STACK_PROTECTOR), 0)
42 PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c
43endif
44
45BL1_SOURCES += drivers/io/io_semihosting.c \
46 drivers/io/io_storage.c \
47 drivers/io/io_fip.c \
48 drivers/io/io_memmap.c \
49 lib/semihosting/semihosting.c \
50 lib/semihosting/${ARCH}/semihosting_call.S \
51 ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
52 ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
53 ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c \
54 ${QEMU_CPU_LIBS}
55
56BL2_SOURCES += drivers/io/io_semihosting.c \
57 drivers/io/io_storage.c \
58 drivers/io/io_fip.c \
59 drivers/io/io_memmap.c \
60 lib/semihosting/semihosting.c \
61 lib/semihosting/${ARCH}/semihosting_call.S \
62 ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
63 ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
64 ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \
65 ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \
66 ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \
67 common/desc_image_load.c \
68 common/fdt_fixup.c
Marcin Juszkiewicz61c99032023-07-24 21:37:00 +020069
70BL31_SOURCES += ${QEMU_CPU_LIBS} \
71 lib/semihosting/semihosting.c \
72 lib/semihosting/${ARCH}/semihosting_call.S \
73 plat/common/plat_psci_common.c \
74 ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
75 ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
76 common/fdt_fixup.c \
77 ${QEMU_GIC_SOURCES}
78
Marcin Juszkiewicz8acc2da2023-07-24 21:44:17 +020079# CPU flag enablement
Marcin Juszkiewicz5aece712023-07-24 22:07:49 +020080ifeq (${ARCH},aarch64)
Marcin Juszkiewicz8acc2da2023-07-24 21:44:17 +020081
Marcin Juszkiewiczc4dae6e2023-11-13 16:18:49 +010082# Cpu core architecture level:
83# v8.0: a53, a57, a72
84# v8.2: a55, a76, n1
85# v8.4: v1
86# v9.0: a710, n2
87#
88#
89# We go v8.0 by default and will enable all features we want
90
91ARM_ARCH_MAJOR := 8
92ARM_ARCH_MINOR := 0
93
94# 8.0
95ENABLE_FEAT_CSV2_2 := 2
96
97# 8.1
98ENABLE_FEAT_PAN := 2
99ENABLE_FEAT_VHE := 2
100
101# 8.2
102# TF-A currently does not permit dynamic detection of FEAT_RAS
103# so this is the only safe setting
104ENABLE_FEAT_RAS := 0
105
106# 8.4
107ENABLE_FEAT_SEL2 := 2
108ENABLE_FEAT_DIT := 2
109
110# 8.5
111ENABLE_FEAT_RNG := 2
Marcin Juszkiewicz69ae7da2024-02-08 12:07:45 +0100112# TF-A currently does not do dynamic detection of FEAT_SB.
113# Compiler puts SB instruction when it is enabled.
114ENABLE_FEAT_SB := 0
Marcin Juszkiewiczc4dae6e2023-11-13 16:18:49 +0100115
116# 8.6
117ENABLE_FEAT_FGT := 2
118
119# 8.7
120ENABLE_FEAT_HCX := 2
121
Marcin Juszkiewicz5aece712023-07-24 22:07:49 +0200122# SPM_MM is not compatible with ENABLE_SVE_FOR_NS (build breaks)
123ifeq (${SPM_MM},1)
124 ENABLE_SVE_FOR_NS := 0
125 ENABLE_SME_FOR_NS := 0
126else
Marcin Juszkiewicz8acc2da2023-07-24 21:44:17 +0200127 ENABLE_SVE_FOR_NS := 2
128 ENABLE_SME_FOR_NS := 2
129endif
130
Jean-Philippe Brucker6125ee42023-09-06 16:18:02 +0100131ifeq (${ENABLE_RME},1)
132BL31_SOURCES += plat/qemu/common/qemu_plat_attest_token.c \
133 plat/qemu/common/qemu_realm_attest_key.c
134endif
135
Marcin Juszkiewicz676443b2023-07-24 21:54:34 +0200136# Treating this as a memory-constrained port for now
137USE_COHERENT_MEM := 0
138
139# This can be overridden depending on CPU(s) used in the QEMU image
140HW_ASSISTED_COHERENCY := 1
141
142CTX_INCLUDE_AARCH32_REGS := 0
143ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
144$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
145endif
Marcin Juszkiewicz1da28d12023-08-21 21:17:12 +0200146
147# Pointer Authentication sources
148ifeq (${ENABLE_PAUTH}, 1)
149PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c
150CTX_INCLUDE_PAUTH_REGS := 1
151endif
152
Marcin Juszkiewicz676443b2023-07-24 21:54:34 +0200153endif