blob: 29fd0eb282a649bea2afa3b410ffd9a26a7bf6bb [file] [log] [blame]
Sieu Mun Tang8881ad02022-03-07 12:04:59 +08001#
2# Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7PLAT_INCLUDES := \
8 -Iplat/intel/soc/n5x/include/ \
9 -Iplat/intel/soc/common/drivers/ \
10 -Iplat/intel/soc/common/include/
11
12# Include GICv2 driver files
13include drivers/arm/gic/v2/gicv2.mk
14DM_GICv2_SOURCES := \
15 ${GICV2_SOURCES} \
16 plat/common/plat_gicv2.c
17
18
19PLAT_BL_COMMON_SOURCES := \
20 ${DM_GICv2_SOURCES} \
21 drivers/delay_timer/delay_timer.c \
22 drivers/delay_timer/generic_delay_timer.c \
23 drivers/ti/uart/aarch64/16550_console.S \
24 lib/xlat_tables/aarch64/xlat_tables.c \
25 lib/xlat_tables/xlat_tables_common.c \
26 plat/intel/soc/common/aarch64/platform_common.c \
27 plat/intel/soc/common/aarch64/plat_helpers.S \
Boon Khai Ng1e5550b2021-05-21 22:56:37 +080028 plat/intel/soc/common/socfpga_delay_timer.c \
29 plat/intel/soc/common/drivers/ccu/ncore_ccu.c
Sieu Mun Tang8881ad02022-03-07 12:04:59 +080030
31BL2_SOURCES +=
32
33BL31_SOURCES += \
34 drivers/arm/cci/cci.c \
35 lib/cpus/aarch64/aem_generic.S \
36 lib/cpus/aarch64/cortex_a53.S \
37 plat/common/plat_psci_common.c \
38 plat/intel/soc/n5x/bl31_plat_setup.c \
Sieu Mun Tangf48707a2022-06-23 18:05:02 +080039 plat/intel/soc/n5x/soc/n5x_clock_manager.c \
Sieu Mun Tang8881ad02022-03-07 12:04:59 +080040 plat/intel/soc/common/socfpga_psci.c \
41 plat/intel/soc/common/socfpga_sip_svc.c \
Sieu Mun Tang044ed482022-05-11 10:45:19 +080042 plat/intel/soc/common/socfpga_sip_svc_v2.c \
Sieu Mun Tang8881ad02022-03-07 12:04:59 +080043 plat/intel/soc/common/socfpga_topology.c \
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +080044 plat/intel/soc/common/sip/socfpga_sip_ecc.c \
Sieu Mun Tang8881ad02022-03-07 12:04:59 +080045 plat/intel/soc/common/sip/socfpga_sip_fcs.c \
46 plat/intel/soc/common/soc/socfpga_mailbox.c \
47 plat/intel/soc/common/soc/socfpga_reset_manager.c
48
Jit Loon Limc5a3e3a2023-10-16 00:19:34 +080049$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
50
Sieu Mun Tang8881ad02022-03-07 12:04:59 +080051PROGRAMMABLE_RESET_ADDRESS := 0
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060052RESET_TO_BL2 := 1
Sieu Mun Tang8881ad02022-03-07 12:04:59 +080053BL2_INV_DCACHE := 0
Sieu Mun Tang8881ad02022-03-07 12:04:59 +080054USE_COHERENT_MEM := 1