| Muhammad Hadi Asyrafi Abdul Halim | c0d4d93 | 2019-03-19 17:59:06 +0800 | [diff] [blame] | 1 | /* |
| Jit Loon Lim | 5080606 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. |
| Muhammad Hadi Asyrafi Abdul Halim | c0d4d93 | 2019-03-19 17:59:06 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| Hadi Asyrafi | c461add | 2019-06-12 11:24:12 +0800 | [diff] [blame] | 7 | #ifndef CAD_WATCHDOG_H |
| 8 | #define CAD_WATCHDOG_H |
| Muhammad Hadi Asyrafi Abdul Halim | c0d4d93 | 2019-03-19 17:59:06 +0800 | [diff] [blame] | 9 | |
| Sieu Mun Tang | 6284537 | 2023-06-09 23:33:36 +0800 | [diff] [blame] | 10 | #include "socfpga_plat_def.h" |
| 11 | |
| Muhammad Hadi Asyrafi Abdul Halim | c0d4d93 | 2019-03-19 17:59:06 +0800 | [diff] [blame] | 12 | #define WDT_REG_SIZE_OFFSET (0x4) |
| 13 | #define WDT_MIN_CYCLES (65536) |
| 14 | #define WDT_PERIOD (20) |
| 15 | |
| 16 | #define WDT_CR (WDT_BASE + 0x0) |
| 17 | #define WDT_TORR (WDT_BASE + 0x4) |
| 18 | |
| 19 | #define WDT_CRR (WDT_BASE + 0xC) |
| 20 | |
| 21 | #define WDT_CCVR (WDT_BASE + 0x8) |
| 22 | #define WDT_STAT (WDT_BASE + 0x10) |
| 23 | #define WDT_EOI (WDT_BASE + 0x14) |
| 24 | |
| 25 | #define WDT_COMP_PARAM_1 (WDT_BASE + 0xF4) |
| 26 | #define WDT_COMP_VERSION (WDT_BASE + 0xF8) |
| 27 | #define WDT_COMP_TYPE (WDT_BASE + 0XFC) |
| 28 | |
| 29 | #define WDT_CR_RMOD (0x0) |
| 30 | #define WDT_CR_EN (0x1) |
| 31 | |
| 32 | #define WDT_SW_RST (0x76) |
| 33 | |
| 34 | |
| 35 | void watchdog_init(int watchdog_clk); |
| Muhammad Hadi Asyrafi Abdul Halim | c0d4d93 | 2019-03-19 17:59:06 +0800 | [diff] [blame] | 36 | void watchdog_info(void); |
| 37 | void watchdog_status(void); |
| 38 | void watchdog_sw_rst(void); |
| 39 | |
| 40 | #endif |