Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 1 | /* |
Govindraj Raja | 776fa58 | 2023-06-15 15:32:41 -0500 | [diff] [blame] | 2 | * Copyright (c) 2019-2023, Arm Limited. All rights reserved. |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 7 | #include <arch.h> |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 8 | #include <asm_macros.S> |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 9 | #include <common/bl_common.h> |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 10 | #include <cortex_a76ae.h> |
| 11 | #include <cpu_macros.S> |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 12 | #include "wa_cve_2022_23960_bhb_vector.S" |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 13 | |
John Tsichritzis | fe6df39 | 2019-03-19 17:20:52 +0000 | [diff] [blame] | 14 | /* Hardware handled coherency */ |
| 15 | #if HW_ASSISTED_COHERENCY == 0 |
| 16 | #error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 17 | #endif |
| 18 | |
John Tsichritzis | 7557c66 | 2019-06-03 13:54:30 +0100 | [diff] [blame] | 19 | /* 64-bit only core */ |
| 20 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 21 | #error "Cortex-A76AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 22 | #endif |
| 23 | |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 24 | #if WORKAROUND_CVE_2022_23960 |
| 25 | wa_cve_2022_23960_bhb_vector_table CORTEX_A76AE_BHB_LOOP_COUNT, cortex_a76ae |
| 26 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 27 | |
Govindraj Raja | 776fa58 | 2023-06-15 15:32:41 -0500 | [diff] [blame] | 28 | check_erratum_chosen cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 29 | |
Govindraj Raja | 776fa58 | 2023-06-15 15:32:41 -0500 | [diff] [blame] | 30 | workaround_reset_start cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 31 | #if IMAGE_BL31 |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 32 | /* |
| 33 | * The Cortex-A76ae generic vectors are overridden to apply errata |
| 34 | * mitigation on exception entry from lower ELs. |
| 35 | */ |
Govindraj Raja | ff525a5 | 2023-06-15 15:34:38 -0500 | [diff] [blame] | 36 | override_vector_table wa_cve_vbar_cortex_a76ae |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 37 | isb |
Govindraj Raja | 776fa58 | 2023-06-15 15:32:41 -0500 | [diff] [blame] | 38 | #endif /* IMAGE_BL31 */ |
| 39 | workaround_reset_end cortex_a76ae, CVE(2022, 23960) |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 40 | |
Govindraj Raja | 776fa58 | 2023-06-15 15:32:41 -0500 | [diff] [blame] | 41 | cpu_reset_func_start cortex_a76ae |
| 42 | cpu_reset_func_end cortex_a76ae |
| 43 | |
| 44 | errata_report_shim cortex_a76ae |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 45 | |
| 46 | /* ---------------------------------------------------- |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 47 | * HW will do the cache maintenance while powering down |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 48 | * ---------------------------------------------------- |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 49 | */ |
| 50 | func cortex_a76ae_core_pwr_dwn |
Govindraj Raja | ff525a5 | 2023-06-15 15:34:38 -0500 | [diff] [blame] | 51 | sysreg_bit_set CORTEX_A76AE_CPUPWRCTLR_EL1, CORTEX_A76AE_CORE_PWRDN_EN_MASK |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 52 | isb |
| 53 | ret |
| 54 | endfunc cortex_a76ae_core_pwr_dwn |
| 55 | |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 56 | /* --------------------------------------------- |
| 57 | * This function provides cortex_a76ae specific |
| 58 | * register information for crash reporting. |
| 59 | * It needs to return with x6 pointing to |
| 60 | * a list of register names in ascii and |
| 61 | * x8 - x15 having values of registers to be |
| 62 | * reported. |
| 63 | * --------------------------------------------- |
| 64 | */ |
| 65 | .section .rodata.cortex_a76ae_regs, "aS" |
| 66 | cortex_a76ae_regs: /* The ASCII list of register names to be reported */ |
| 67 | .asciz "cpuectlr_el1", "" |
| 68 | |
| 69 | func cortex_a76ae_cpu_reg_dump |
| 70 | adr x6, cortex_a76ae_regs |
| 71 | mrs x8, CORTEX_A76AE_CPUECTLR_EL1 |
| 72 | ret |
| 73 | endfunc cortex_a76ae_cpu_reg_dump |
| 74 | |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 75 | declare_cpu_ops cortex_a76ae, CORTEX_A76AE_MIDR, cortex_a76ae_reset_func, \ |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 76 | cortex_a76ae_core_pwr_dwn |