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git01.mediatek.com / filogic / atf / 89c586b69136a2366d5991c6d42c6b4809362f2a / . / drivers / synopsys / ufs / dw_ufs.c
blob: 6bed981db0b6f647dc1c1b12d0636343886c428e [file] [log] [blame]
Haojian Zhuang93494ae2017-05-31 11:00:46 -0600[diff] [blame]1/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
Haojian Zhuang93494ae2017-05-31 11:00:46 -0600[diff] [blame]8#include <stdint.h>
9#include <string.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]10
11#include <common/debug.h>
12#include <drivers/dw_ufs.h>
13#include <drivers/ufs.h>
14#include <lib/mmio.h>
Haojian Zhuang93494ae2017-05-31 11:00:46 -0600[diff] [blame]15
16static int dwufs_phy_init(ufs_params_t *params)
17{
18 uintptr_t base;
19 unsigned int fsm0, fsm1;
20 unsigned int data;
21 int result;
22
23 assert((params != NULL) && (params->reg_base != 0));
24
25 base = params->reg_base;
26
27 /* Unipro VS_MPHY disable */
28 ufshc_dme_set(VS_MPHY_DISABLE_OFFSET, 0, VS_MPHY_DISABLE_MPHYDIS);
29 ufshc_dme_set(PA_HS_SERIES_OFFSET, 0, 2);
30 /* MPHY CBRATESEL */
31 ufshc_dme_set(0x8114, 0, 1);
32 /* MPHY CBOVRCTRL2 */
33 ufshc_dme_set(0x8121, 0, 0x2d);
34 /* MPHY CBOVRCTRL3 */
35 ufshc_dme_set(0x8122, 0, 0x1);
36 ufshc_dme_set(VS_MPHY_CFG_UPDT_OFFSET, 0, 1);
37
38 /* MPHY RXOVRCTRL4 rx0 */
39 ufshc_dme_set(0x800d, 4, 0x58);
40 /* MPHY RXOVRCTRL4 rx1 */
41 ufshc_dme_set(0x800d, 5, 0x58);
42 /* MPHY RXOVRCTRL5 rx0 */
43 ufshc_dme_set(0x800e, 4, 0xb);
44 /* MPHY RXOVRCTRL5 rx1 */
45 ufshc_dme_set(0x800e, 5, 0xb);
46 /* MPHY RXSQCONTROL rx0 */
47 ufshc_dme_set(0x8009, 4, 0x1);
48 /* MPHY RXSQCONTROL rx1 */
49 ufshc_dme_set(0x8009, 5, 0x1);
50 ufshc_dme_set(VS_MPHY_CFG_UPDT_OFFSET, 0, 1);
51
52 ufshc_dme_set(0x8113, 0, 0x1);
53 ufshc_dme_set(VS_MPHY_CFG_UPDT_OFFSET, 0, 1);
54
55 ufshc_dme_set(RX_HS_G3_SYNC_LENGTH_CAP_OFFSET, 4, 0x4a);
56 ufshc_dme_set(RX_HS_G3_SYNC_LENGTH_CAP_OFFSET, 5, 0x4a);
57 ufshc_dme_set(RX_HS_G2_SYNC_LENGTH_CAP_OFFSET, 4, 0x4a);
58 ufshc_dme_set(RX_HS_G2_SYNC_LENGTH_CAP_OFFSET, 5, 0x4a);
59 ufshc_dme_set(RX_MIN_ACTIVATETIME_CAP_OFFSET, 4, 0x7);
60 ufshc_dme_set(RX_MIN_ACTIVATETIME_CAP_OFFSET, 5, 0x7);
61 ufshc_dme_set(TX_HIBERN8TIME_CAP_OFFSET, 0, 0x5);
62 ufshc_dme_set(TX_HIBERN8TIME_CAP_OFFSET, 1, 0x5);
63 ufshc_dme_set(VS_MPHY_CFG_UPDT_OFFSET, 0, 1);
64
65 result = ufshc_dme_get(VS_MPHY_DISABLE_OFFSET, 0, &data);
66 assert((result == 0) && (data == VS_MPHY_DISABLE_MPHYDIS));
67 /* enable Unipro VS MPHY */
68 ufshc_dme_set(VS_MPHY_DISABLE_OFFSET, 0, 0);
69
70 while (1) {
71 result = ufshc_dme_get(TX_FSM_STATE_OFFSET, 0, &fsm0);
72 assert(result == 0);
73 result = ufshc_dme_get(TX_FSM_STATE_OFFSET, 1, &fsm1);
74 assert(result == 0);
75 if ((fsm0 == TX_FSM_STATE_HIBERN8) &&
76 (fsm1 == TX_FSM_STATE_HIBERN8))
77 break;
78 }
79
80 mmio_write_32(base + HCLKDIV, 0xE4);
81 mmio_clrbits_32(base + AHIT, 0x3FF);
82
83 ufshc_dme_set(PA_LOCAL_TX_LCC_ENABLE_OFFSET, 0, 0);
84 ufshc_dme_set(VS_MK2_EXTN_SUPPORT_OFFSET, 0, 0);
85
86 result = ufshc_dme_get(VS_MK2_EXTN_SUPPORT_OFFSET, 0, &data);
87 assert((result == 0) && (data == 0));
88
89 ufshc_dme_set(DL_AFC0_CREDIT_THRESHOLD_OFFSET, 0, 0);
90 ufshc_dme_set(DL_TC0_OUT_ACK_THRESHOLD_OFFSET, 0, 0);
91 ufshc_dme_set(DL_TC0_TX_FC_THRESHOLD_OFFSET, 0, 9);
92 (void)result;
93 return 0;
94}
95
96static int dwufs_phy_set_pwr_mode(ufs_params_t *params)
97{
98 int result;
99 unsigned int data, tx_lanes, rx_lanes;
100 uintptr_t base;
fengbaopeng44070ef2018-02-12 20:53:54 +0800[diff] [blame]101 unsigned int flags;
Haojian Zhuang93494ae2017-05-31 11:00:46 -0600[diff] [blame]102
103 assert((params != NULL) && (params->reg_base != 0));
104
105 base = params->reg_base;
fengbaopeng44070ef2018-02-12 20:53:54 +0800[diff] [blame]106 flags = params->flags;
107 if ((flags & UFS_FLAGS_VENDOR_SKHYNIX) != 0U) {
108 NOTICE("ufs: H**** device must set VS_DebugSaveConfigTime 0x10\n");
109 /* VS_DebugSaveConfigTime */
110 result = ufshc_dme_set(0xd0a0, 0x0, 0x10);
111 assert(result == 0);
112 /* sync length */
113 result = ufshc_dme_set(0x1556, 0x0, 0x48);
114 assert(result == 0);
115 }
Haojian Zhuang93494ae2017-05-31 11:00:46 -0600[diff] [blame]116
117 result = ufshc_dme_get(PA_TACTIVATE_OFFSET, 0, &data);
118 assert(result == 0);
119 if (data < 7) {
120 result = ufshc_dme_set(PA_TACTIVATE_OFFSET, 0, 7);
121 assert(result == 0);
122 }
123 result = ufshc_dme_get(PA_CONNECTED_TX_DATA_LANES_OFFSET, 0, &tx_lanes);
124 assert(result == 0);
125 result = ufshc_dme_get(PA_CONNECTED_RX_DATA_LANES_OFFSET, 0, &rx_lanes);
126 assert(result == 0);
127
128 result = ufshc_dme_set(PA_TX_SKIP_OFFSET, 0, 0);
129 assert(result == 0);
130 result = ufshc_dme_set(PA_TX_GEAR_OFFSET, 0, 3);
131 assert(result == 0);
132 result = ufshc_dme_set(PA_RX_GEAR_OFFSET, 0, 3);
133 assert(result == 0);
134 result = ufshc_dme_set(PA_HS_SERIES_OFFSET, 0, 2);
135 assert(result == 0);
136 result = ufshc_dme_set(PA_TX_TERMINATION_OFFSET, 0, 1);
137 assert(result == 0);
138 result = ufshc_dme_set(PA_RX_TERMINATION_OFFSET, 0, 1);
139 assert(result == 0);
140 result = ufshc_dme_set(PA_SCRAMBLING_OFFSET, 0, 0);
141 assert(result == 0);
142 result = ufshc_dme_set(PA_ACTIVE_TX_DATA_LANES_OFFSET, 0, tx_lanes);
143 assert(result == 0);
144 result = ufshc_dme_set(PA_ACTIVE_RX_DATA_LANES_OFFSET, 0, rx_lanes);
145 assert(result == 0);
146 result = ufshc_dme_set(PA_PWR_MODE_USER_DATA0_OFFSET, 0, 8191);
147 assert(result == 0);
148 result = ufshc_dme_set(PA_PWR_MODE_USER_DATA1_OFFSET, 0, 65535);
149 assert(result == 0);
150 result = ufshc_dme_set(PA_PWR_MODE_USER_DATA2_OFFSET, 0, 32767);
151 assert(result == 0);
152 result = ufshc_dme_set(DME_FC0_PROTECTION_TIMEOUT_OFFSET, 0, 8191);
153 assert(result == 0);
154 result = ufshc_dme_set(DME_TC0_REPLAY_TIMEOUT_OFFSET, 0, 65535);
155 assert(result == 0);
156 result = ufshc_dme_set(DME_AFC0_REQ_TIMEOUT_OFFSET, 0, 32767);
157 assert(result == 0);
158 result = ufshc_dme_set(PA_PWR_MODE_USER_DATA3_OFFSET, 0, 8191);
159 assert(result == 0);
160 result = ufshc_dme_set(PA_PWR_MODE_USER_DATA4_OFFSET, 0, 65535);
161 assert(result == 0);
162 result = ufshc_dme_set(PA_PWR_MODE_USER_DATA5_OFFSET, 0, 32767);
163 assert(result == 0);
164 result = ufshc_dme_set(DME_FC1_PROTECTION_TIMEOUT_OFFSET, 0, 8191);
165 assert(result == 0);
166 result = ufshc_dme_set(DME_TC1_REPLAY_TIMEOUT_OFFSET, 0, 65535);
167 assert(result == 0);
168 result = ufshc_dme_set(DME_AFC1_REQ_TIMEOUT_OFFSET, 0, 32767);
169 assert(result == 0);
170
171 result = ufshc_dme_set(PA_PWR_MODE_OFFSET, 0, 0x11);
172 assert(result == 0);
173 do {
174 data = mmio_read_32(base + IS);
175 } while ((data & UFS_INT_UPMS) == 0);
176 mmio_write_32(base + IS, UFS_INT_UPMS);
177 data = mmio_read_32(base + HCS);
178 if ((data & HCS_UPMCRS_MASK) == HCS_PWR_LOCAL)
179 INFO("ufs: change power mode success\n");
180 else
181 WARN("ufs: HCS.UPMCRS error, HCS:0x%x\n", data);
182 (void)result;
183 return 0;
184}
185
Florian La Roche231c2442019-01-27 14:30:12 +0100[diff] [blame]186static const ufs_ops_t dw_ufs_ops = {
Haojian Zhuang93494ae2017-05-31 11:00:46 -0600[diff] [blame]187 .phy_init = dwufs_phy_init,
188 .phy_set_pwr_mode = dwufs_phy_set_pwr_mode,
189};
190
191int dw_ufs_init(dw_ufs_params_t *params)
192{
193 ufs_params_t ufs_params;
194
195 memset(&ufs_params, 0, sizeof(ufs_params));
196 ufs_params.reg_base = params->reg_base;
197 ufs_params.desc_base = params->desc_base;
198 ufs_params.desc_size = params->desc_size;
199 ufs_params.flags = params->flags;
200 ufs_init(&dw_ufs_ops, &ufs_params);
201 return 0;
202}