blob: aba15df1220e01700c15a39e2e2a768332744b85 [file] [log] [blame]
Soby Mathewc6820d12016-05-09 17:49:55 +01001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __ARCH_H__
32#define __ARCH_H__
33
34/*******************************************************************************
35 * MIDR bit definitions
36 ******************************************************************************/
37#define MIDR_IMPL_MASK 0xff
38#define MIDR_IMPL_SHIFT 24
39#define MIDR_VAR_SHIFT 20
40#define MIDR_VAR_BITS 4
41#define MIDR_REV_SHIFT 0
42#define MIDR_REV_BITS 4
43#define MIDR_PN_MASK 0xfff
44#define MIDR_PN_SHIFT 4
45
46/*******************************************************************************
47 * MPIDR macros
48 ******************************************************************************/
49#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
50#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
51#define MPIDR_AFFINITY_BITS 8
52#define MPIDR_AFFLVL_MASK 0xff
53#define MPIDR_AFFLVL_SHIFT 3
54#define MPIDR_AFF0_SHIFT 0
55#define MPIDR_AFF1_SHIFT 8
56#define MPIDR_AFF2_SHIFT 16
57#define MPIDR_AFFINITY_MASK 0x00ffffff
58#define MPIDR_AFFLVL0 0
59#define MPIDR_AFFLVL1 1
60#define MPIDR_AFFLVL2 2
61
62#define MPIDR_AFFLVL0_VAL(mpidr) \
63 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
64#define MPIDR_AFFLVL1_VAL(mpidr) \
65 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
66#define MPIDR_AFFLVL2_VAL(mpidr) \
67 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
68
69/*
70 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
71 * add one while using this macro to define array sizes.
72 */
73#define MPIDR_MAX_AFFLVL 2
74
75/* Data Cache set/way op type defines */
76#define DC_OP_ISW 0x0
77#define DC_OP_CISW 0x1
78#define DC_OP_CSW 0x2
79
80/*******************************************************************************
81 * Generic timer memory mapped registers & offsets
82 ******************************************************************************/
83#define CNTCR_OFF 0x000
84#define CNTFID_OFF 0x020
85
86#define CNTCR_EN (1 << 0)
87#define CNTCR_HDBG (1 << 1)
88#define CNTCR_FCREQ(x) ((x) << 8)
89
90/*******************************************************************************
91 * System register bit definitions
92 ******************************************************************************/
93/* CLIDR definitions */
94#define LOUIS_SHIFT 21
95#define LOC_SHIFT 24
96#define CLIDR_FIELD_WIDTH 3
97
98/* CSSELR definitions */
99#define LEVEL_SHIFT 1
100
101/* ID_PFR1 definitions */
102#define ID_PFR1_VIRTEXT_SHIFT 12
103#define ID_PFR1_VIRTEXT_MASK 0xf
104#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
105 & ID_PFR1_VIRTEXT_MASK)
106#define ID_PFR1_GIC_SHIFT 28
107#define ID_PFR1_GIC_MASK 0xf
108
109/* SCTLR definitions */
110#define SCTLR_RES1 ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \
111 (1 << 3) | SCTLR_CP15BEN_BIT | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT)
112#define SCTLR_M_BIT (1 << 0)
113#define SCTLR_A_BIT (1 << 1)
114#define SCTLR_C_BIT (1 << 2)
115#define SCTLR_CP15BEN_BIT (1 << 5)
116#define SCTLR_ITD_BIT (1 << 7)
117#define SCTLR_I_BIT (1 << 12)
118#define SCTLR_V_BIT (1 << 13)
119#define SCTLR_NTWI_BIT (1 << 16)
120#define SCTLR_NTWE_BIT (1 << 18)
121#define SCTLR_WXN_BIT (1 << 19)
122#define SCTLR_UWXN_BIT (1 << 20)
123#define SCTLR_EE_BIT (1 << 25)
124#define SCTLR_TRE_BIT (1 << 28)
125#define SCTLR_AFE_BIT (1 << 29)
126#define SCTLR_TE_BIT (1 << 30)
127
128/* HSCTLR definitions */
129#define HSCTLR_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) \
130 | (1 << 18) | (1 << 16) | (1 << 11) | (1 << 4) \
131 | (1 << 3) | HSCTLR_CP15BEN_BIT)
132#define HSCTLR_M_BIT (1 << 0)
133#define HSCTLR_A_BIT (1 << 1)
134#define HSCTLR_C_BIT (1 << 2)
135#define HSCTLR_CP15BEN_BIT (1 << 5)
136#define HSCTLR_ITD_BIT (1 << 7)
137#define HSCTLR_SED_BIT (1 << 8)
138#define HSCTLR_I_BIT (1 << 12)
139#define HSCTLR_WXN_BIT (1 << 19)
140#define HSCTLR_EE_BIT (1 << 25)
141#define HSCTLR_TE_BIT (1 << 30)
142
143/* CPACR definitions */
144#define CPACR_FPEN(x) ((x) << 20)
145#define CPACR_FP_TRAP_PL0 0x1
146#define CPACR_FP_TRAP_ALL 0x2
147#define CPACR_FP_TRAP_NONE 0x3
148
149/* SCR definitions */
150#define SCR_TWE_BIT (1 << 13)
151#define SCR_TWI_BIT (1 << 12)
152#define SCR_SIF_BIT (1 << 9)
153#define SCR_HCE_BIT (1 << 8)
154#define SCR_SCD_BIT (1 << 7)
155#define SCR_NET_BIT (1 << 6)
156#define SCR_AW_BIT (1 << 5)
157#define SCR_FW_BIT (1 << 4)
158#define SCR_EA_BIT (1 << 3)
159#define SCR_FIQ_BIT (1 << 2)
160#define SCR_IRQ_BIT (1 << 1)
161#define SCR_NS_BIT (1 << 0)
162#define SCR_VALID_BIT_MASK 0x33ff
163
164#define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT)
165
166/* HCR definitions */
167#define HCR_AMO_BIT (1 << 5)
168#define HCR_IMO_BIT (1 << 4)
169#define HCR_FMO_BIT (1 << 3)
170
171/* CNTHCTL definitions */
172#define EVNTEN_BIT (1 << 2)
173#define PL1PCEN_BIT (1 << 1)
174#define PL1PCTEN_BIT (1 << 0)
175
176/* CNTKCTL definitions */
177#define PL0PTEN_BIT (1 << 9)
178#define PL0VTEN_BIT (1 << 8)
179#define PL0PCTEN_BIT (1 << 0)
180#define PL0VCTEN_BIT (1 << 1)
181#define EVNTEN_BIT (1 << 2)
182#define EVNTDIR_BIT (1 << 3)
183#define EVNTI_SHIFT 4
184#define EVNTI_MASK 0xf
185
186/* HCPTR definitions */
187#define TCPAC_BIT (1 << 31)
188#define TTA_BIT (1 << 20)
189#define TCP11_BIT (1 << 10)
190#define TCP10_BIT (1 << 10)
191
192/* NASCR definitions */
193#define NSASEDIS_BIT (1 << 15)
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100194#define NSTRCDIS_BIT (1 << 20)
Soby Mathewc6820d12016-05-09 17:49:55 +0100195#define NASCR_CP11_BIT (1 << 11)
196#define NASCR_CP10_BIT (1 << 10)
197
198/* CPACR definitions */
199#define ASEDIS_BIT (1 << 31)
200#define TRCDIS_BIT (1 << 28)
201#define CPACR_CP11_SHIFT 22
202#define CPACR_CP10_SHIFT 20
203#define CPACR_ENABLE_FP_ACCESS (0x3 << CPACR_CP11_SHIFT |\
204 0x3 << CPACR_CP10_SHIFT)
205
206/* FPEXC definitions */
207#define FPEXC_EN_BIT (1 << 30)
208
209/* SPSR/CPSR definitions */
210#define SPSR_FIQ_BIT (1 << 0)
211#define SPSR_IRQ_BIT (1 << 1)
212#define SPSR_ABT_BIT (1 << 2)
213#define SPSR_AIF_SHIFT 6
214#define SPSR_AIF_MASK 0x7
215
216#define SPSR_E_SHIFT 9
217#define SPSR_E_MASK 0x1
218#define SPSR_E_LITTLE 0
219#define SPSR_E_BIG 1
220
221#define SPSR_T_SHIFT 5
222#define SPSR_T_MASK 0x1
223#define SPSR_T_ARM 0
224#define SPSR_T_THUMB 1
225
226#define SPSR_MODE_SHIFT 0
227#define SPSR_MODE_MASK 0x7
228
229
230#define DISABLE_ALL_EXCEPTIONS \
231 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
232
233/*
234 * TTBCR definitions
235 */
236/* The ARM Trusted Firmware uses the long descriptor format */
237#define TTBCR_EAE_BIT (1 << 31)
238
239#define TTBCR_SH1_NON_SHAREABLE (0x0 << 28)
240#define TTBCR_SH1_OUTER_SHAREABLE (0x2 << 28)
241#define TTBCR_SH1_INNER_SHAREABLE (0x3 << 28)
242
243#define TTBCR_RGN1_OUTER_NC (0x0 << 26)
244#define TTBCR_RGN1_OUTER_WBA (0x1 << 26)
245#define TTBCR_RGN1_OUTER_WT (0x2 << 26)
246#define TTBCR_RGN1_OUTER_WBNA (0x3 << 26)
247
248#define TTBCR_RGN1_INNER_NC (0x0 << 24)
249#define TTBCR_RGN1_INNER_WBA (0x1 << 24)
250#define TTBCR_RGN1_INNER_WT (0x2 << 24)
251#define TTBCR_RGN1_INNER_WBNA (0x3 << 24)
252
253#define TTBCR_EPD1_BIT (1 << 23)
254#define TTBCR_A1_BIT (1 << 22)
255
256#define TTBCR_T1SZ_SHIFT 16
257#define TTBCR_T1SZ_MASK (0x7)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100258#define TTBCR_TxSZ_MIN 0
259#define TTBCR_TxSZ_MAX 7
Soby Mathewc6820d12016-05-09 17:49:55 +0100260
261#define TTBCR_SH0_NON_SHAREABLE (0x0 << 12)
262#define TTBCR_SH0_OUTER_SHAREABLE (0x2 << 12)
263#define TTBCR_SH0_INNER_SHAREABLE (0x3 << 12)
264
265#define TTBCR_RGN0_OUTER_NC (0x0 << 10)
266#define TTBCR_RGN0_OUTER_WBA (0x1 << 10)
267#define TTBCR_RGN0_OUTER_WT (0x2 << 10)
268#define TTBCR_RGN0_OUTER_WBNA (0x3 << 10)
269
270#define TTBCR_RGN0_INNER_NC (0x0 << 8)
271#define TTBCR_RGN0_INNER_WBA (0x1 << 8)
272#define TTBCR_RGN0_INNER_WT (0x2 << 8)
273#define TTBCR_RGN0_INNER_WBNA (0x3 << 8)
274
275#define TTBCR_EPD0_BIT (1 << 7)
276#define TTBCR_T0SZ_SHIFT 0
277#define TTBCR_T0SZ_MASK (0x7)
278
279#define MODE_RW_SHIFT 0x4
280#define MODE_RW_MASK 0x1
281#define MODE_RW_32 0x1
282
283#define MODE32_SHIFT 0
284#define MODE32_MASK 0x1f
285#define MODE32_usr 0x10
286#define MODE32_fiq 0x11
287#define MODE32_irq 0x12
288#define MODE32_svc 0x13
289#define MODE32_mon 0x16
290#define MODE32_abt 0x17
291#define MODE32_hyp 0x1a
292#define MODE32_und 0x1b
293#define MODE32_sys 0x1f
294
295#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
296
297#define SPSR_MODE32(mode, isa, endian, aif) \
298 (MODE_RW_32 << MODE_RW_SHIFT | \
299 ((mode) & MODE32_MASK) << MODE32_SHIFT | \
300 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
301 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
302 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
303
304/*
305 * CTR definitions
306 */
307#define CTR_CWG_SHIFT 24
308#define CTR_CWG_MASK 0xf
309#define CTR_ERG_SHIFT 20
310#define CTR_ERG_MASK 0xf
311#define CTR_DMINLINE_SHIFT 16
312#define CTR_DMINLINE_WIDTH 4
313#define CTR_DMINLINE_MASK ((1 << 4) - 1)
314#define CTR_L1IP_SHIFT 14
315#define CTR_L1IP_MASK 0x3
316#define CTR_IMINLINE_SHIFT 0
317#define CTR_IMINLINE_MASK 0xf
318
319#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */
320
321/*******************************************************************************
322 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
323 * system level implementation of the Generic Timer.
324 ******************************************************************************/
325#define CNTNSAR 0x4
326#define CNTNSAR_NS_SHIFT(x) (x)
327
328#define CNTACR_BASE(x) (0x40 + ((x) << 2))
329#define CNTACR_RPCT_SHIFT 0x0
330#define CNTACR_RVCT_SHIFT 0x1
331#define CNTACR_RFRQ_SHIFT 0x2
332#define CNTACR_RVOFF_SHIFT 0x3
333#define CNTACR_RWVT_SHIFT 0x4
334#define CNTACR_RWPT_SHIFT 0x5
335
336/* MAIR macros */
337#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << 3))
338#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - 3) << 3))
339
340/* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
341#define SCR p15, 0, c1, c1, 0
342#define SCTLR p15, 0, c1, c0, 0
343#define MPIDR p15, 0, c0, c0, 5
344#define MIDR p15, 0, c0, c0, 0
345#define VBAR p15, 0, c12, c0, 0
346#define MVBAR p15, 0, c12, c0, 1
347#define NSACR p15, 0, c1, c1, 2
348#define CPACR p15, 0, c1, c0, 2
349#define DCCIMVAC p15, 0, c7, c14, 1
350#define DCCMVAC p15, 0, c7, c10, 1
351#define DCIMVAC p15, 0, c7, c6, 1
352#define DCCISW p15, 0, c7, c14, 2
353#define DCCSW p15, 0, c7, c10, 2
354#define DCISW p15, 0, c7, c6, 2
355#define CTR p15, 0, c0, c0, 1
356#define CNTFRQ p15, 0, c14, c0, 0
357#define ID_PFR1 p15, 0, c0, c1, 1
358#define MAIR0 p15, 0, c10, c2, 0
359#define MAIR1 p15, 0, c10, c2, 1
360#define TTBCR p15, 0, c2, c0, 2
361#define TTBR0 p15, 0, c2, c0, 0
362#define TTBR1 p15, 0, c2, c0, 1
363#define TLBIALL p15, 0, c8, c7, 0
364#define TLBIALLIS p15, 0, c8, c3, 0
365#define TLBIMVA p15, 0, c8, c7, 1
366#define TLBIMVAA p15, 0, c8, c7, 3
367#define HSCTLR p15, 4, c1, c0, 0
368#define HCR p15, 4, c1, c1, 0
369#define HCPTR p15, 4, c1, c1, 2
370#define CNTHCTL p15, 4, c14, c1, 0
371#define VPIDR p15, 4, c0, c0, 0
372#define VMPIDR p15, 4, c0, c0, 5
373#define ISR p15, 0, c12, c1, 0
374#define CLIDR p15, 1, c0, c0, 1
375#define CSSELR p15, 2, c0, c0, 0
376#define CCSIDR p15, 1, c0, c0, 0
377
378/* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
379#define ICC_IAR1 p15, 0, c12, c12, 0
380#define ICC_IAR0 p15, 0, c12, c8, 0
381#define ICC_EOIR1 p15, 0, c12, c12, 1
382#define ICC_EOIR0 p15, 0, c12, c8, 1
383#define ICC_HPPIR1 p15, 0, c12, c12, 2
384#define ICC_HPPIR0 p15, 0, c12, c8, 2
385#define ICC_BPR1 p15, 0, c12, c12, 3
386#define ICC_BPR0 p15, 0, c12, c8, 3
387#define ICC_DIR p15, 0, c12, c11, 1
388#define ICC_PMR p15, 0, c4, c6, 0
389#define ICC_RPR p15, 0, c12, c11, 3
390#define ICC_CTLR p15, 0, c12, c12, 4
391#define ICC_MCTLR p15, 6, c12, c12, 4
392#define ICC_SRE p15, 0, c12, c12, 5
393#define ICC_HSRE p15, 4, c12, c9, 5
394#define ICC_MSRE p15, 6, c12, c12, 5
395#define ICC_IGRPEN0 p15, 0, c12, c12, 6
396#define ICC_IGRPEN1 p15, 0, c12, c12, 7
397#define ICC_MGRPEN1 p15, 6, c12, c12, 7
398
399/* 64 bit system register defines The format is: coproc, opt1, CRm */
400#define TTBR0_64 p15, 0, c2
401#define TTBR1_64 p15, 1, c2
402#define CNTVOFF_64 p15, 4, c14
403#define VTTBR_64 p15, 6, c2
404#define CNTPCT_64 p15, 0, c14
405
406/* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */
407#define ICC_SGI1R_EL1_64 p15, 0, c12
408#define ICC_ASGI1R_EL1_64 p15, 1, c12
409#define ICC_SGI0R_EL1_64 p15, 2, c12
410
411#endif /* __ARCH_H__ */