blob: c7d3c12ef211274dadf2856756057b24ae4f0680 [file] [log] [blame]
Yatharth Kochar5d361212016-06-28 17:07:09 +01001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch_helpers.h>
32#include <assert.h>
33#include <context.h>
34#include <context_mgmt.h>
35#include <debug.h>
36#include <platform.h>
37#include <smcc_helpers.h>
38
39/*
40 * Following arrays will be used for context management.
41 * There are 2 instances, for the Secure and Non-Secure contexts.
42 */
43static cpu_context_t bl1_cpu_context[2];
44static smc_ctx_t bl1_smc_context[2];
45
46/* Following contains the next cpu context pointer. */
47static void *bl1_next_cpu_context_ptr;
48
49/* Following contains the next smc context pointer. */
50static void *bl1_next_smc_context_ptr;
51
52/* Following functions are used for SMC context handling */
53void *smc_get_ctx(int security_state)
54{
55 assert(sec_state_is_valid(security_state));
56 return &bl1_smc_context[security_state];
57}
58
59void smc_set_next_ctx(int security_state)
60{
61 assert(sec_state_is_valid(security_state));
62 bl1_next_smc_context_ptr = &bl1_smc_context[security_state];
63}
64
65void *smc_get_next_ctx(void)
66{
67 return bl1_next_smc_context_ptr;
68}
69
70/* Following functions are used for CPU context handling */
71void *cm_get_context(uint32_t security_state)
72{
73 assert(sec_state_is_valid(security_state));
74 return &bl1_cpu_context[security_state];
75}
76
77void cm_set_next_context(void *cpu_context)
78{
79 assert(cpu_context);
80 bl1_next_cpu_context_ptr = cpu_context;
81}
82
83void *cm_get_next_context(void)
84{
85 return bl1_next_cpu_context_ptr;
86}
87
88/*******************************************************************************
89 * Following function copies GP regs r0-r4, lr and spsr,
90 * from the CPU context to the SMC context structures.
91 ******************************************************************************/
92static void copy_cpu_ctx_to_smc_ctx(const regs_t *cpu_reg_ctx,
93 smc_ctx_t *next_smc_ctx)
94{
95 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0);
96 next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1);
97 next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2);
98 next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3);
99 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR);
100 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR);
101}
102
103/*******************************************************************************
104 * Following function flushes the SMC & CPU context pointer and its data.
105 ******************************************************************************/
106static void flush_smc_and_cpu_ctx(void)
107{
108 flush_dcache_range((uintptr_t)&bl1_next_smc_context_ptr,
109 sizeof(bl1_next_smc_context_ptr));
110 flush_dcache_range((uintptr_t)bl1_next_smc_context_ptr,
111 sizeof(smc_ctx_t));
112
113 flush_dcache_range((uintptr_t)&bl1_next_cpu_context_ptr,
114 sizeof(bl1_next_cpu_context_ptr));
115 flush_dcache_range((uintptr_t)bl1_next_cpu_context_ptr,
116 sizeof(cpu_context_t));
117}
118
119/*******************************************************************************
120 * This function prepares the context for Secure/Normal world images.
121 * Normal world images are transitioned to HYP(if supported) else SVC.
122 ******************************************************************************/
123void bl1_prepare_next_image(unsigned int image_id)
124{
125 unsigned int security_state;
126 image_desc_t *image_desc;
127 entry_point_info_t *next_bl_ep;
128
129 /* Get the image descriptor. */
130 image_desc = bl1_plat_get_image_desc(image_id);
131 assert(image_desc);
132
133 /* Get the entry point info. */
134 next_bl_ep = &image_desc->ep_info;
135
136 /* Get the image security state. */
137 security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
138
139 /* Prepare the SPSR for the next BL image. */
140 if (security_state == SECURE) {
141 next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
142 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
143 } else {
144 /* Use HYP mode if supported else use SVC. */
145 if (GET_VIRT_EXT(read_id_pfr1()) == MODE32_hyp) {
146 next_bl_ep->spsr = SPSR_MODE32(MODE32_hyp, SPSR_T_ARM,
147 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
148 } else {
149 next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
150 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
151 }
152 }
153
154 /* Allow platform to make change */
155 bl1_plat_set_ep_info(image_id, next_bl_ep);
156
157 /* Prepare the cpu context for the next BL image. */
158 cm_init_my_context(next_bl_ep);
159 cm_prepare_el3_exit(security_state);
160 cm_set_next_context(cm_get_context(security_state));
161
162 /* Prepare the smc context for the next BL image. */
163 smc_set_next_ctx(security_state);
164 copy_cpu_ctx_to_smc_ctx(get_regs_ctx(cm_get_next_context()),
165 smc_get_next_ctx());
166
167 /*
168 * Flush the SMC & CPU context and the (next)pointers,
169 * to access them after caches are disabled.
170 */
171 flush_smc_and_cpu_ctx();
172
173 /* Indicate that image is in execution state. */
174 image_desc->state = IMAGE_STATE_EXECUTED;
175
176 print_entry_point_info(next_bl_ep);
177}