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Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +02001/*
Biju Das08d33082020-12-13 19:41:27 +00002 * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef EMMC_REGISTERS_H
8#define EMMC_REGISTERS_H
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +02009
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +020010/* MMC channel select */
11#define MMC_CH0 (0U) /* SDHI2/MMC0 */
12#define MMC_CH1 (1U) /* SDHI3/MMC1 */
13
Lad Prabhakar5cf699c2021-03-18 18:55:49 +000014#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2M) || (RCAR_LSI == RZ_G2H) || (RCAR_LSI == RZ_G2N)
15#define USE_MMC_CH (MMC_CH1) /* R-Car E3 or RZ/G2{H,M,N} */
16#else /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2{H,M,N} */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +020017#define USE_MMC_CH (MMC_CH0) /* R-Car H3/M3/M3N */
Lad Prabhakar5cf699c2021-03-18 18:55:49 +000018#endif /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2{H,M,N} */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +020019
Biju Das08d33082020-12-13 19:41:27 +000020#define BIT0 (0x00000001U)
21#define BIT1 (0x00000002U)
22#define BIT2 (0x00000004U)
23#define BIT3 (0x00000008U)
24#define BIT4 (0x00000010U)
25#define BIT5 (0x00000020U)
26#define BIT6 (0x00000040U)
27#define BIT7 (0x00000080U)
28#define BIT8 (0x00000100U)
29#define BIT9 (0x00000200U)
30#define BIT10 (0x00000400U)
31#define BIT11 (0x00000800U)
32#define BIT12 (0x00001000U)
33#define BIT13 (0x00002000U)
34#define BIT14 (0x00004000U)
35#define BIT15 (0x00008000U)
36#define BIT16 (0x00010000U)
37#define BIT17 (0x00020000U)
38#define BIT18 (0x00040000U)
39#define BIT19 (0x00080000U)
40#define BIT20 (0x00100000U)
41#define BIT21 (0x00200000U)
42#define BIT22 (0x00400000U)
43#define BIT23 (0x00800000U)
44#define BIT24 (0x01000000U)
45#define BIT25 (0x02000000U)
46#define BIT26 (0x04000000U)
47#define BIT27 (0x08000000U)
48#define BIT28 (0x10000000U)
49#define BIT29 (0x20000000U)
50#define BIT30 (0x40000000U)
51#define BIT31 (0x80000000U)
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +020052
Biju Das08d33082020-12-13 19:41:27 +000053/* Clock Pulse Generator (CPG) registers */
54#define CPG_BASE (0xE6150000U)
55/* Module stop status register 3 */
56#define CPG_MSTPSR3 (CPG_BASE + 0x0048U)
57/* System module stop control register 3 */
58#define CPG_SMSTPCR3 (CPG_BASE + 0x013CU)
59/* SDHI2 clock frequency control register */
60#define CPG_SD2CKCR (CPG_BASE + 0x0268U)
61/* SDHI3 clock frequency control register */
62#define CPG_SD3CKCR (CPG_BASE + 0x026CU)
63/* CPG Write Protect Register */
64#define CPG_CPGWPR (CPG_BASE + 0x0900U)
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +020065
66#if USE_MMC_CH == MMC_CH0
Biju Das08d33082020-12-13 19:41:27 +000067#define CPG_SDxCKCR (CPG_SD2CKCR) /* SDHI2/MMC0 */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +020068#else /* USE_MMC_CH == MMC_CH0 */
Biju Das08d33082020-12-13 19:41:27 +000069#define CPG_SDxCKCR (CPG_SD3CKCR) /* SDHI3/MMC1 */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +020070#endif /* USE_MMC_CH == MMC_CH0 */
71
Biju Das08d33082020-12-13 19:41:27 +000072/* Boot Status register */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +020073#define MFISBTSTSR (0xE6260604U)
74
75#define MFISBTSTSR_BOOT_PARTITION (0x00000010U)
76
Biju Das08d33082020-12-13 19:41:27 +000077/* eMMC registers */
78#define MMC0_SD_BASE (0xEE140000U)
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +020079#define MMC1_SD_BASE (0xEE160000U)
80
81#if USE_MMC_CH == MMC_CH0
Biju Das08d33082020-12-13 19:41:27 +000082#define MMC_SD_BASE (MMC0_SD_BASE)
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +020083#else /* USE_MMC_CH == MMC_CH0 */
Biju Das08d33082020-12-13 19:41:27 +000084#define MMC_SD_BASE (MMC1_SD_BASE)
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +020085#endif /* USE_MMC_CH == MMC_CH0 */
86
87#define SD_CMD (MMC_SD_BASE + 0x0000U)
88#define SD_PORTSEL (MMC_SD_BASE + 0x0008U)
89#define SD_ARG (MMC_SD_BASE + 0x0010U)
90#define SD_ARG1 (MMC_SD_BASE + 0x0018U)
91#define SD_STOP (MMC_SD_BASE + 0x0020U)
92#define SD_SECCNT (MMC_SD_BASE + 0x0028U)
93#define SD_RSP10 (MMC_SD_BASE + 0x0030U)
94#define SD_RSP1 (MMC_SD_BASE + 0x0038U)
95#define SD_RSP32 (MMC_SD_BASE + 0x0040U)
96#define SD_RSP3 (MMC_SD_BASE + 0x0048U)
97#define SD_RSP54 (MMC_SD_BASE + 0x0050U)
98#define SD_RSP5 (MMC_SD_BASE + 0x0058U)
99#define SD_RSP76 (MMC_SD_BASE + 0x0060U)
100#define SD_RSP7 (MMC_SD_BASE + 0x0068U)
101#define SD_INFO1 (MMC_SD_BASE + 0x0070U)
102#define SD_INFO2 (MMC_SD_BASE + 0x0078U)
103#define SD_INFO1_MASK (MMC_SD_BASE + 0x0080U)
104#define SD_INFO2_MASK (MMC_SD_BASE + 0x0088U)
105#define SD_CLK_CTRL (MMC_SD_BASE + 0x0090U)
106#define SD_SIZE (MMC_SD_BASE + 0x0098U)
107#define SD_OPTION (MMC_SD_BASE + 0x00A0U)
108#define SD_ERR_STS1 (MMC_SD_BASE + 0x00B0U)
109#define SD_ERR_STS2 (MMC_SD_BASE + 0x00B8U)
110#define SD_BUF0 (MMC_SD_BASE + 0x00C0U)
111#define SDIO_MODE (MMC_SD_BASE + 0x00D0U)
112#define SDIO_INFO1 (MMC_SD_BASE + 0x00D8U)
113#define SDIO_INFO1_MASK (MMC_SD_BASE + 0x00E0U)
114#define CC_EXT_MODE (MMC_SD_BASE + 0x0360U)
115#define SOFT_RST (MMC_SD_BASE + 0x0380U)
116#define VERSION (MMC_SD_BASE + 0x0388U)
117#define HOST_MODE (MMC_SD_BASE + 0x0390U)
118#define DM_CM_DTRAN_MODE (MMC_SD_BASE + 0x0820U)
119#define DM_CM_DTRAN_CTRL (MMC_SD_BASE + 0x0828U)
120#define DM_CM_RST (MMC_SD_BASE + 0x0830U)
121#define DM_CM_INFO1 (MMC_SD_BASE + 0x0840U)
122#define DM_CM_INFO1_MASK (MMC_SD_BASE + 0x0848U)
123#define DM_CM_INFO2 (MMC_SD_BASE + 0x0850U)
124#define DM_CM_INFO2_MASK (MMC_SD_BASE + 0x0858U)
125#define DM_DTRAN_ADDR (MMC_SD_BASE + 0x0880U)
126
Biju Das08d33082020-12-13 19:41:27 +0000127/* SD_INFO1 Registers */
128#define SD_INFO1_HPIRES 0x00010000UL /* Response Reception Completion */
129#define SD_INFO1_INFO10 0x00000400UL /* Indicates the SDDAT3 state */
130#define SD_INFO1_INFO9 0x00000200UL /* SDDAT3 Card Insertion */
131#define SD_INFO1_INFO8 0x00000100UL /* SDDAT3 Card Removal */
132#define SD_INFO1_INFO7 0x00000080UL /* Write Protect */
133#define SD_INFO1_INFO5 0x00000020UL /* Indicates the ISDCD state */
134#define SD_INFO1_INFO4 0x00000010UL /* ISDCD Card Insertion */
135#define SD_INFO1_INFO3 0x00000008UL /* ISDCD Card Removal */
136#define SD_INFO1_INFO2 0x00000004UL /* Access end */
137#define SD_INFO1_INFO0 0x00000001UL /* Response end */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +0200138
Biju Das08d33082020-12-13 19:41:27 +0000139/* SD_INFO2 Registers */
140#define SD_INFO2_ILA 0x00008000UL /* Illegal Access Error */
141#define SD_INFO2_CBSY 0x00004000UL /* Command Type Register Busy */
142#define SD_INFO2_SCLKDIVEN 0x00002000UL
143#define SD_INFO2_BWE 0x00000200UL /* SD_BUF Write Enable */
144#define SD_INFO2_BRE 0x00000100UL /* SD_BUF Read Enable */
145#define SD_INFO2_DAT0 0x00000080UL /* SDDAT0 */
146#define SD_INFO2_ERR6 0x00000040UL /* Response Timeout */
147#define SD_INFO2_ERR5 0x00000020UL /* SD_BUF Illegal Read Access */
148#define SD_INFO2_ERR4 0x00000010UL /* SD_BUF Illegal Write Access */
149#define SD_INFO2_ERR3 0x00000008UL /* Data Timeout */
150#define SD_INFO2_ERR2 0x00000004UL /* END Error */
151#define SD_INFO2_ERR1 0x00000002UL /* CRC Error */
152#define SD_INFO2_ERR0 0x00000001UL /* CMD Error */
153#define SD_INFO2_ALL_ERR 0x0000807FUL
154#define SD_INFO2_CLEAR 0x00000800UL /* BIT11 write value should always be 1. HWM_0003 */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +0200155
Biju Das08d33082020-12-13 19:41:27 +0000156/* SOFT_RST */
157#define SOFT_RST_SDRST 0x00000001UL
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +0200158
Biju Das08d33082020-12-13 19:41:27 +0000159/* SD_CLK_CTRL */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +0200160#define SD_CLK_CTRL_SDCLKOFFEN 0x00000200UL
Biju Das08d33082020-12-13 19:41:27 +0000161#define SD_CLK_CTRL_SCLKEN 0x00000100UL
162#define SD_CLK_CTRL_CLKDIV_MASK 0x000000FFUL
163#define SD_CLOCK_ENABLE 0x00000100UL
164#define SD_CLOCK_DISABLE 0x00000000UL
165#define SD_CLK_WRITE_MASK 0x000003FFUL
166#define SD_CLK_CLKDIV_CLEAR_MASK 0xFFFFFF0FUL
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +0200167
Biju Das08d33082020-12-13 19:41:27 +0000168/* SD_OPTION */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +0200169#define SD_OPTION_TIMEOUT_CNT_MASK 0x000000F0UL
170
Biju Das08d33082020-12-13 19:41:27 +0000171/*
172 * MMC Clock Frequency
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +0200173 * 200MHz * 1/x = output clock
174 */
Biju Das08d33082020-12-13 19:41:27 +0000175#define MMC_CLK_OFF 0UL /* Clock output is disabled */
176#define MMC_400KHZ 512UL /* 200MHz * 1/512 = 390 KHz */
177#define MMC_20MHZ 16UL /* 200MHz * 1/16 = 12.5 MHz Normal speed mode */
178#define MMC_26MHZ 8UL /* 200MHz * 1/8 = 25 MHz HS mode 26Mhz */
179#define MMC_52MHZ 4UL /* 200MHz * 1/4 = 50 MHz HS mode 52Mhz */
180#define MMC_100MHZ 2UL /* 200MHz * 1/2 = 100 MHz */
181#define MMC_200MHZ 1UL /* 200MHz * 1/1 = 200 MHz */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +0200182
183#define MMC_FREQ_52MHZ 52000000UL
184#define MMC_FREQ_26MHZ 26000000UL
185#define MMC_FREQ_20MHZ 20000000UL
186
Biju Das08d33082020-12-13 19:41:27 +0000187/* MMC Clock DIV */
188#define MMC_SD_CLK_START 0x00000100UL /* CLOCK On */
189#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */
190#define MMC_SD_CLK_DIV1 0x000000FFUL /* 1/1 */
191#define MMC_SD_CLK_DIV2 0x00000000UL /* 1/2 */
192#define MMC_SD_CLK_DIV4 0x00000001UL /* 1/4 */
193#define MMC_SD_CLK_DIV8 0x00000002UL /* 1/8 */
194#define MMC_SD_CLK_DIV16 0x00000004UL /* 1/16 */
195#define MMC_SD_CLK_DIV32 0x00000008UL /* 1/32 */
196#define MMC_SD_CLK_DIV64 0x00000010UL /* 1/64 */
197#define MMC_SD_CLK_DIV128 0x00000020UL /* 1/128 */
198#define MMC_SD_CLK_DIV256 0x00000040UL /* 1/256 */
199#define MMC_SD_CLK_DIV512 0x00000080UL /* 1/512 */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +0200200
Biju Das08d33082020-12-13 19:41:27 +0000201/* DM_CM_DTRAN_MODE */
202#define DM_CM_DTRAN_MODE_CH0 0x00000000UL /* CH0(downstream) */
203#define DM_CM_DTRAN_MODE_CH1 0x00010000UL /* CH1(upstream) */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +0200204#define DM_CM_DTRAN_MODE_BIT_WIDTH 0x00000030UL
205
Biju Das08d33082020-12-13 19:41:27 +0000206/* CC_EXT_MODE */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +0200207#define CC_EXT_MODE_DMASDRW_ENABLE 0x00000002UL /* SD_BUF Read/Write DMA Transfer */
Biju Das08d33082020-12-13 19:41:27 +0000208#define CC_EXT_MODE_CLEAR 0x00001010UL /* BIT 12 & 4 always 1. */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +0200209
Biju Das08d33082020-12-13 19:41:27 +0000210/* DM_CM_INFO_MASK */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +0200211#define DM_CM_INFO_MASK_CLEAR 0xFFFCFFFEUL
212#define DM_CM_INFO_CH0_ENABLE 0x00010001UL
213#define DM_CM_INFO_CH1_ENABLE 0x00020001UL
214
Biju Das08d33082020-12-13 19:41:27 +0000215/* DM_DTRAN_ADDR */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +0200216#define DM_DTRAN_ADDR_WRITE_MASK 0xFFFFFFF8UL
217
Biju Das08d33082020-12-13 19:41:27 +0000218/* DM_CM_DTRAN_CTRL */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +0200219#define DM_CM_DTRAN_CTRL_START 0x00000001UL
220
Biju Das08d33082020-12-13 19:41:27 +0000221/* SYSC Registers */
Jorge Ramirez-Ortiz766263c2018-09-23 09:39:56 +0200222#if USE_MMC_CH == MMC_CH0
223#define CPG_MSTP_MMC (BIT12) /* SDHI2/MMC0 */
224#else /* USE_MMC_CH == MMC_CH0 */
225#define CPG_MSTP_MMC (BIT11) /* SDHI3/MMC1 */
226#endif /* USE_MMC_CH == MMC_CH0 */
227
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000228#endif /* EMMC_REGISTERS_H */