Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __PLATFORM_DEF_H__ |
| 8 | #define __PLATFORM_DEF_H__ |
| 9 | |
| 10 | #include <arch.h> |
Xing Zheng | c39aacd | 2016-12-22 18:34:14 +0800 | [diff] [blame] | 11 | #include <bl31_param.h> |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 12 | #include <common_def.h> |
| 13 | #include <rk3399_def.h> |
| 14 | |
| 15 | #define DEBUG_XLAT_TABLE 0 |
| 16 | |
| 17 | /******************************************************************************* |
| 18 | * Platform binary types for linking |
| 19 | ******************************************************************************/ |
| 20 | #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" |
| 21 | #define PLATFORM_LINKER_ARCH aarch64 |
| 22 | |
| 23 | /******************************************************************************* |
| 24 | * Generic platform constants |
| 25 | ******************************************************************************/ |
| 26 | |
| 27 | /* Size of cacheable stacks */ |
| 28 | #if DEBUG_XLAT_TABLE |
| 29 | #define PLATFORM_STACK_SIZE 0x800 |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 30 | #elif defined(IMAGE_BL1) |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 31 | #define PLATFORM_STACK_SIZE 0x440 |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 32 | #elif defined(IMAGE_BL2) |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 33 | #define PLATFORM_STACK_SIZE 0x400 |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 34 | #elif defined(IMAGE_BL31) |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 35 | #define PLATFORM_STACK_SIZE 0x800 |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 36 | #elif defined(IMAGE_BL32) |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 37 | #define PLATFORM_STACK_SIZE 0x440 |
| 38 | #endif |
| 39 | |
| 40 | #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" |
| 41 | |
| 42 | #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 |
| 43 | #define PLATFORM_SYSTEM_COUNT 1 |
| 44 | #define PLATFORM_CLUSTER_COUNT 2 |
| 45 | #define PLATFORM_CLUSTER0_CORE_COUNT 4 |
| 46 | #define PLATFORM_CLUSTER1_CORE_COUNT 2 |
| 47 | #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ |
| 48 | PLATFORM_CLUSTER0_CORE_COUNT) |
| 49 | #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 |
| 50 | #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ |
| 51 | PLATFORM_CLUSTER_COUNT + \ |
| 52 | PLATFORM_CORE_COUNT) |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 53 | #define PLAT_RK_CLST_TO_CPUID_SHIFT 6 |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 54 | #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 |
| 55 | |
| 56 | /* |
| 57 | * This macro defines the deepest retention state possible. A higher state |
| 58 | * id will represent an invalid or a power down state. |
| 59 | */ |
| 60 | #define PLAT_MAX_RET_STATE 1 |
| 61 | |
| 62 | /* |
| 63 | * This macro defines the deepest power down states possible. Any state ID |
| 64 | * higher than this is invalid. |
| 65 | */ |
| 66 | #define PLAT_MAX_OFF_STATE 2 |
| 67 | |
| 68 | /******************************************************************************* |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 69 | * Platform specific page table and MMU setup constants |
| 70 | ******************************************************************************/ |
| 71 | #define ADDR_SPACE_SIZE (1ull << 32) |
| 72 | #define MAX_XLAT_TABLES 20 |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 73 | #define MAX_MMAP_REGIONS 25 |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 74 | |
| 75 | /******************************************************************************* |
| 76 | * Declarations and constants to access the mailboxes safely. Each mailbox is |
| 77 | * aligned on the biggest cache line size in the platform. This is known only |
| 78 | * to the platform as it might have a combination of integrated and external |
| 79 | * caches. Such alignment ensures that two maiboxes do not sit on the same cache |
| 80 | * line at any cache level. They could belong to different cpus/clusters & |
| 81 | * get written while being protected by different locks causing corruption of |
| 82 | * a valid mailbox address. |
| 83 | ******************************************************************************/ |
| 84 | #define CACHE_WRITEBACK_SHIFT 6 |
| 85 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 86 | |
| 87 | /* |
| 88 | * Define GICD and GICC and GICR base |
| 89 | */ |
| 90 | #define PLAT_RK_GICD_BASE BASE_GICD_BASE |
| 91 | #define PLAT_RK_GICR_BASE BASE_GICR_BASE |
| 92 | #define PLAT_RK_GICC_BASE 0 |
| 93 | |
| 94 | /* |
| 95 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 96 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 97 | * as Group 0 interrupts. |
| 98 | */ |
| 99 | #define PLAT_RK_G1S_IRQS RK3399_G1S_IRQS |
| 100 | #define PLAT_RK_G0_IRQS RK3399_G0_IRQS |
| 101 | |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 102 | #define PLAT_RK_UART_BASE UART2_BASE |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 103 | #define PLAT_RK_UART_CLOCK RK3399_UART_CLOCK |
| 104 | #define PLAT_RK_UART_BAUDRATE RK3399_BAUDRATE |
| 105 | |
| 106 | #define PLAT_RK_CCI_BASE CCI500_BASE |
| 107 | |
| 108 | #define PLAT_RK_PRIMARY_CPU 0x0 |
| 109 | |
Lin Huang | 30e4339 | 2017-05-04 16:02:45 +0800 | [diff] [blame] | 110 | #define PSRAM_DO_DDR_RESUME 1 |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 111 | #endif /* __PLATFORM_DEF_H__ */ |