Heiko Stuebner | 87b9a3c | 2019-03-14 22:12:04 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| 8 | |
| 9 | #include <arch_helpers.h> |
| 10 | #include <common/debug.h> |
| 11 | #include <drivers/delay_timer.h> |
| 12 | |
| 13 | #include <plat_private.h> |
| 14 | #include <secure.h> |
| 15 | #include <soc.h> |
| 16 | |
| 17 | static void sgrf_ddr_rgn_global_bypass(uint32_t bypass) |
| 18 | { |
| 19 | if (bypass) |
| 20 | /* set bypass (non-secure regions) for whole ddr regions */ |
| 21 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(21), |
| 22 | SGRF_DDR_RGN_BYPS); |
| 23 | else |
| 24 | /* cancel bypass for whole ddr regions */ |
| 25 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(21), |
| 26 | SGRF_DDR_RGN_NO_BYPS); |
| 27 | } |
| 28 | |
| 29 | /** |
| 30 | * There are 8 + 1 regions for DDR secure control: |
| 31 | * DDR_RGN_0 ~ DDR_RGN_7: Per DDR_RGNs grain size is 1MB |
| 32 | * DDR_RGN_X - the memories of exclude DDR_RGN_0 ~ DDR_RGN_7 |
| 33 | * |
| 34 | * SGRF_SOC_CON6 - start address of RGN_0 + control |
| 35 | * SGRF_SOC_CON7 - end address of RGN_0 |
| 36 | * ... |
| 37 | * SGRF_SOC_CON20 - start address of the RGN_7 + control |
| 38 | * SGRF_SOC_CON21 - end address of the RGN_7 + RGN_X control |
| 39 | * |
| 40 | * @rgn - the DDR regions 0 ~ 7 which are can be configured. |
| 41 | * The @st and @ed indicate the start and end addresses for which to set |
| 42 | * the security, and the unit is byte. When the st_mb == 0, ed_mb == 0, the |
| 43 | * address range 0x0 ~ 0xfffff is secure. |
| 44 | * |
| 45 | * For example, if we would like to set the range [0, 32MB) is security via |
| 46 | * DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31. |
| 47 | */ |
| 48 | static void sgrf_ddr_rgn_config(uint32_t rgn, uintptr_t st, uintptr_t ed) |
| 49 | { |
| 50 | uintptr_t st_mb, ed_mb; |
| 51 | |
| 52 | assert(rgn <= 7); |
| 53 | assert(st < ed); |
| 54 | |
| 55 | /* check aligned 1MB */ |
| 56 | assert(st % SIZE_M(1) == 0); |
| 57 | assert(ed % SIZE_M(1) == 0); |
| 58 | |
| 59 | st_mb = st / SIZE_M(1); |
| 60 | ed_mb = ed / SIZE_M(1); |
| 61 | |
| 62 | /* set ddr region addr start */ |
| 63 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), |
| 64 | BITS_WITH_WMASK(st_mb, SGRF_DDR_RGN_ADDR_WMSK, 0)); |
| 65 | |
| 66 | /* set ddr region addr end */ |
| 67 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2) + 1), |
| 68 | BITS_WITH_WMASK((ed_mb - 1), SGRF_DDR_RGN_ADDR_WMSK, 0)); |
| 69 | |
| 70 | /* select region security */ |
| 71 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), |
| 72 | SGRF_DDR_RGN_SECURE_SEL); |
| 73 | |
| 74 | /* enable region security */ |
| 75 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), |
| 76 | SGRF_DDR_RGN_SECURE_EN); |
| 77 | } |
| 78 | |
| 79 | void secure_watchdog_gate(void) |
| 80 | { |
| 81 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), SGRF_PCLK_WDT_GATE); |
| 82 | } |
| 83 | |
| 84 | void secure_watchdog_ungate(void) |
| 85 | { |
| 86 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), SGRF_PCLK_WDT_UNGATE); |
| 87 | } |
| 88 | |
| 89 | __pmusramfunc void sram_secure_timer_init(void) |
| 90 | { |
| 91 | mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, 0); |
| 92 | |
| 93 | mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT0, 0xffffffff); |
| 94 | mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT1, 0xffffffff); |
| 95 | |
| 96 | /* auto reload & enable the timer */ |
| 97 | mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); |
| 98 | } |
| 99 | |
| 100 | void secure_gic_init(void) |
| 101 | { |
| 102 | /* (re-)enable non-secure access to the gic*/ |
| 103 | mmio_write_32(CORE_AXI_BUS_BASE + CORE_AXI_SECURITY0, |
| 104 | AXI_SECURITY0_GIC); |
| 105 | } |
| 106 | |
| 107 | void secure_timer_init(void) |
| 108 | { |
| 109 | mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, 0); |
| 110 | |
| 111 | mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT0, 0xffffffff); |
| 112 | mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT1, 0xffffffff); |
| 113 | |
| 114 | /* auto reload & enable the timer */ |
| 115 | mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); |
| 116 | } |
| 117 | |
| 118 | void secure_sgrf_init(void) |
| 119 | { |
| 120 | /* |
| 121 | * We use the first sram part to talk to the bootrom, |
| 122 | * so make it secure. |
| 123 | */ |
| 124 | mmio_write_32(TZPC_BASE + TZPC_R0SIZE, TZPC_SRAM_SECURE_4K(1)); |
| 125 | |
| 126 | secure_gic_init(); |
| 127 | |
| 128 | /* set all master ip to non-secure */ |
| 129 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), SGRF_SOC_CON2_MST_NS); |
| 130 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), SGRF_SOC_CON3_MST_NS); |
| 131 | |
| 132 | /* setting all configurable ip into non-secure */ |
| 133 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), |
| 134 | SGRF_SOC_CON4_SECURE_WMSK /*TODO:|SGRF_STIMER_SECURE*/); |
| 135 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SOC_CON5_SECURE_WMSK); |
| 136 | |
| 137 | /* secure dma to non-secure */ |
| 138 | mmio_write_32(TZPC_BASE + TZPC_DECPROT1SET, 0xff); |
| 139 | mmio_write_32(TZPC_BASE + TZPC_DECPROT2SET, 0xff); |
| 140 | mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(1), 0x3800); |
| 141 | dsb(); |
| 142 | |
| 143 | /* rst dma1 */ |
| 144 | mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), |
| 145 | RST_DMA1_MSK | (RST_DMA1_MSK << 16)); |
| 146 | /* rst dma2 */ |
| 147 | mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), |
| 148 | RST_DMA2_MSK | (RST_DMA2_MSK << 16)); |
| 149 | |
| 150 | dsb(); |
| 151 | |
| 152 | /* release dma1 rst*/ |
| 153 | mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), (RST_DMA1_MSK << 16)); |
| 154 | /* release dma2 rst*/ |
| 155 | mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), (RST_DMA2_MSK << 16)); |
| 156 | } |
| 157 | |
| 158 | void secure_sgrf_ddr_rgn_init(void) |
| 159 | { |
| 160 | sgrf_ddr_rgn_config(0, TZRAM_BASE, TZRAM_SIZE); |
| 161 | sgrf_ddr_rgn_global_bypass(0); |
| 162 | } |