blob: 0e9c270432c5409f72ef455eb0cb0319f18bdb28 [file] [log] [blame]
Rex-BC Chenabd9ecf2021-10-06 19:25:50 +08001/*
jason-ch chena07e3ea2021-11-16 10:18:46 +08002 * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
Rex-BC Chenabd9ecf2021-10-06 19:25:50 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/debug.h>
8#include <common/runtime_svc.h>
developerc9d2bfa2022-06-22 19:51:41 +08009#include <lib/mmio.h>
10#include <mt_msdc.h>
jason-ch chena07e3ea2021-11-16 10:18:46 +080011#include <mt_spm_vcorefs.h>
12#include <mtk_sip_svc.h>
Rex-BC Chen1782ce92021-12-02 14:03:44 +080013#include <plat_dfd.h>
jason-ch chena07e3ea2021-11-16 10:18:46 +080014#include "plat_sip_calls.h"
Rex-BC Chenabd9ecf2021-10-06 19:25:50 +080015
16uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
17 u_register_t x1,
18 u_register_t x2,
19 u_register_t x3,
20 u_register_t x4,
21 void *cookie,
22 void *handle,
23 u_register_t flags)
24{
jason-ch chena07e3ea2021-11-16 10:18:46 +080025 uint64_t ret;
26
Rex-BC Chenabd9ecf2021-10-06 19:25:50 +080027 switch (smc_fid) {
developer8c327e82022-05-29 22:25:44 +080028 case MTK_SIP_VCORE_CONTROL_AARCH32:
29 case MTK_SIP_VCORE_CONTROL_AARCH64:
jason-ch chena07e3ea2021-11-16 10:18:46 +080030 ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4);
31 SMC_RET2(handle, ret, x4);
32 break;
Rex-BC Chen1782ce92021-12-02 14:03:44 +080033 case MTK_SIP_KERNEL_DFD_AARCH32:
34 case MTK_SIP_KERNEL_DFD_AARCH64:
35 ret = dfd_smc_dispatcher(x1, x2, x3, x4);
36 SMC_RET1(handle, ret);
37 break;
developerc9d2bfa2022-06-22 19:51:41 +080038 case MTK_SIP_KERNEL_MSDC_AARCH32:
39 case MTK_SIP_KERNEL_MSDC_AARCH64:
40 ret = msdc_smc_dispatcher(x1, x2, x3, x4);
41 SMC_RET1(handle, ret);
42 break;
Rex-BC Chenabd9ecf2021-10-06 19:25:50 +080043 default:
44 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
45 break;
46 }
47
48 SMC_RET1(handle, SMC_UNK);
49}