| Yann Gautier | 6638695 | 2018-07-05 16:49:51 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
| 2 | /* |
| Patrick Delaunay | a0f6ff7 | 2021-04-30 17:31:52 +0200 | [diff] [blame] | 3 | * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved |
| Yann Gautier | 6638695 | 2018-07-05 16:49:51 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| Nicolas Le Bayon | 5d8e64b | 2021-02-25 11:03:53 +0100 | [diff] [blame] | 6 | &ddr { |
| 7 | st,mem-name = DDR_MEM_NAME; |
| 8 | st,mem-speed = <DDR_MEM_SPEED>; |
| 9 | st,mem-size = <DDR_MEM_SIZE>; |
| Yann Gautier | 6638695 | 2018-07-05 16:49:51 +0200 | [diff] [blame] | 10 | |
| Nicolas Le Bayon | 5d8e64b | 2021-02-25 11:03:53 +0100 | [diff] [blame] | 11 | st,ctl-reg = < |
| 12 | DDR_MSTR |
| 13 | DDR_MRCTRL0 |
| 14 | DDR_MRCTRL1 |
| 15 | DDR_DERATEEN |
| 16 | DDR_DERATEINT |
| 17 | DDR_PWRCTL |
| 18 | DDR_PWRTMG |
| 19 | DDR_HWLPCTL |
| 20 | DDR_RFSHCTL0 |
| 21 | DDR_RFSHCTL3 |
| 22 | DDR_CRCPARCTL0 |
| 23 | DDR_ZQCTL0 |
| 24 | DDR_DFITMG0 |
| 25 | DDR_DFITMG1 |
| 26 | DDR_DFILPCFG0 |
| 27 | DDR_DFIUPD0 |
| 28 | DDR_DFIUPD1 |
| 29 | DDR_DFIUPD2 |
| 30 | DDR_DFIPHYMSTR |
| 31 | DDR_ODTMAP |
| 32 | DDR_DBG0 |
| 33 | DDR_DBG1 |
| 34 | DDR_DBGCMD |
| 35 | DDR_POISONCFG |
| 36 | DDR_PCCFG |
| 37 | >; |
| Yann Gautier | 6638695 | 2018-07-05 16:49:51 +0200 | [diff] [blame] | 38 | |
| Nicolas Le Bayon | 5d8e64b | 2021-02-25 11:03:53 +0100 | [diff] [blame] | 39 | st,ctl-timing = < |
| 40 | DDR_RFSHTMG |
| 41 | DDR_DRAMTMG0 |
| 42 | DDR_DRAMTMG1 |
| 43 | DDR_DRAMTMG2 |
| 44 | DDR_DRAMTMG3 |
| 45 | DDR_DRAMTMG4 |
| 46 | DDR_DRAMTMG5 |
| 47 | DDR_DRAMTMG6 |
| 48 | DDR_DRAMTMG7 |
| 49 | DDR_DRAMTMG8 |
| 50 | DDR_DRAMTMG14 |
| 51 | DDR_ODTCFG |
| 52 | >; |
| Yann Gautier | 6638695 | 2018-07-05 16:49:51 +0200 | [diff] [blame] | 53 | |
| Nicolas Le Bayon | 5d8e64b | 2021-02-25 11:03:53 +0100 | [diff] [blame] | 54 | st,ctl-map = < |
| 55 | DDR_ADDRMAP1 |
| 56 | DDR_ADDRMAP2 |
| 57 | DDR_ADDRMAP3 |
| 58 | DDR_ADDRMAP4 |
| 59 | DDR_ADDRMAP5 |
| 60 | DDR_ADDRMAP6 |
| 61 | DDR_ADDRMAP9 |
| 62 | DDR_ADDRMAP10 |
| 63 | DDR_ADDRMAP11 |
| 64 | >; |
| Yann Gautier | 6638695 | 2018-07-05 16:49:51 +0200 | [diff] [blame] | 65 | |
| Nicolas Le Bayon | 5d8e64b | 2021-02-25 11:03:53 +0100 | [diff] [blame] | 66 | st,ctl-perf = < |
| 67 | DDR_SCHED |
| 68 | DDR_SCHED1 |
| 69 | DDR_PERFHPR1 |
| 70 | DDR_PERFLPR1 |
| 71 | DDR_PERFWR1 |
| 72 | DDR_PCFGR_0 |
| 73 | DDR_PCFGW_0 |
| 74 | DDR_PCFGQOS0_0 |
| 75 | DDR_PCFGQOS1_0 |
| 76 | DDR_PCFGWQOS0_0 |
| 77 | DDR_PCFGWQOS1_0 |
| 78 | DDR_PCFGR_1 |
| 79 | DDR_PCFGW_1 |
| 80 | DDR_PCFGQOS0_1 |
| 81 | DDR_PCFGQOS1_1 |
| 82 | DDR_PCFGWQOS0_1 |
| 83 | DDR_PCFGWQOS1_1 |
| 84 | >; |
| Yann Gautier | 6638695 | 2018-07-05 16:49:51 +0200 | [diff] [blame] | 85 | |
| Nicolas Le Bayon | 5d8e64b | 2021-02-25 11:03:53 +0100 | [diff] [blame] | 86 | st,phy-reg = < |
| 87 | DDR_PGCR |
| 88 | DDR_ACIOCR |
| 89 | DDR_DXCCR |
| 90 | DDR_DSGCR |
| 91 | DDR_DCR |
| 92 | DDR_ODTCR |
| 93 | DDR_ZQ0CR1 |
| 94 | DDR_DX0GCR |
| 95 | DDR_DX1GCR |
| 96 | DDR_DX2GCR |
| 97 | DDR_DX3GCR |
| 98 | >; |
| Yann Gautier | 6638695 | 2018-07-05 16:49:51 +0200 | [diff] [blame] | 99 | |
| Nicolas Le Bayon | 5d8e64b | 2021-02-25 11:03:53 +0100 | [diff] [blame] | 100 | st,phy-timing = < |
| 101 | DDR_PTR0 |
| 102 | DDR_PTR1 |
| 103 | DDR_PTR2 |
| 104 | DDR_DTPR0 |
| 105 | DDR_DTPR1 |
| 106 | DDR_DTPR2 |
| 107 | DDR_MR0 |
| 108 | DDR_MR1 |
| 109 | DDR_MR2 |
| 110 | DDR_MR3 |
| 111 | >; |
| Yann Gautier | 6638695 | 2018-07-05 16:49:51 +0200 | [diff] [blame] | 112 | }; |