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Caesar Wangc1bf6462016-06-21 14:44:01 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Caesar Wangc1bf6462016-06-21 14:44:01 +08005 */
6
Ziyuan Xu4060cfd2017-02-10 11:54:52 +08007#include <cdn_dp.h>
Caesar Wangc1bf6462016-06-21 14:44:01 +08008#include <debug.h>
Isla Mitchelle3631462017-07-14 10:46:32 +01009#include <dfs.h>
Caesar Wangc1bf6462016-06-21 14:44:01 +080010#include <mmio.h>
11#include <plat_sip_calls.h>
12#include <rockchip_sip_svc.h>
13#include <runtime_svc.h>
Paul Kocialkowski2dde8502017-12-02 16:41:38 +010014#include <stdint.h>
Caesar Wang9740bba2016-08-25 08:37:42 +080015
Caesar Wang251a34d2016-09-10 06:25:29 +080016#define RK_SIP_DDR_CFG 0x82000008
17#define DRAM_INIT 0x00
18#define DRAM_SET_RATE 0x01
19#define DRAM_ROUND_RATE 0x02
20#define DRAM_SET_AT_SR 0x03
21#define DRAM_GET_BW 0x04
22#define DRAM_GET_RATE 0x05
23#define DRAM_CLR_IRQ 0x06
24#define DRAM_SET_PARAM 0x07
Derek Basehoreff461d02016-10-20 20:46:43 -070025#define DRAM_SET_ODT_PD 0x08
Caesar Wang9740bba2016-08-25 08:37:42 +080026
Ziyuan Xu4060cfd2017-02-10 11:54:52 +080027#define RK_SIP_HDCP_CONTROL 0x82000009
28#define RK_SIP_HDCP_KEY_DATA64 0xC200000A
29
Derek Basehoreff461d02016-10-20 20:46:43 -070030uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1,
31 uint64_t id, uint64_t arg2)
Caesar Wang9740bba2016-08-25 08:37:42 +080032{
33 switch (id) {
Caesar Wang251a34d2016-09-10 06:25:29 +080034 case DRAM_SET_RATE:
35 return ddr_set_rate((uint32_t)arg0);
36 case DRAM_ROUND_RATE:
37 return ddr_round_rate((uint32_t)arg0);
38 case DRAM_GET_RATE:
Caesar Wang9740bba2016-08-25 08:37:42 +080039 return ddr_get_rate();
Derek Basehoreff461d02016-10-20 20:46:43 -070040 case DRAM_SET_ODT_PD:
41 dram_set_odt_pd(arg0, arg1, arg2);
Caesar Wang9740bba2016-08-25 08:37:42 +080042 break;
43 default:
44 break;
45 }
46
47 return 0;
48}
Caesar Wangc1bf6462016-06-21 14:44:01 +080049
Masahiro Yamada5ac9d962018-04-19 01:18:48 +090050uintptr_t rockchip_plat_sip_handler(uint32_t smc_fid,
51 u_register_t x1,
52 u_register_t x2,
53 u_register_t x3,
54 u_register_t x4,
55 void *cookie,
56 void *handle,
57 u_register_t flags)
Caesar Wangc1bf6462016-06-21 14:44:01 +080058{
Ziyuan Xu4060cfd2017-02-10 11:54:52 +080059 uint64_t x5, x6;
60
Caesar Wangc1bf6462016-06-21 14:44:01 +080061 switch (smc_fid) {
Caesar Wang251a34d2016-09-10 06:25:29 +080062 case RK_SIP_DDR_CFG:
Derek Basehoreff461d02016-10-20 20:46:43 -070063 SMC_RET1(handle, ddr_smc_handler(x1, x2, x3, x4));
Ziyuan Xu4060cfd2017-02-10 11:54:52 +080064 case RK_SIP_HDCP_CONTROL:
65 SMC_RET1(handle, dp_hdcp_ctrl(x1));
66 case RK_SIP_HDCP_KEY_DATA64:
67 x5 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X5);
68 x6 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X6);
69 SMC_RET1(handle, dp_hdcp_store_key(x1, x2, x3, x4, x5, x6));
Caesar Wangc1bf6462016-06-21 14:44:01 +080070 default:
71 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
72 SMC_RET1(handle, SMC_UNK);
73 }
74}