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Chandni Cherukurif3a6cab2020-09-22 18:56:25 +05301/*
Manoj Kumarb19e62a2021-08-26 10:49:02 +05302 * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
Chandni Cherukurif3a6cab2020-09-22 18:56:25 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Manoj Kumar58876122021-01-10 16:12:24 +00007#include <assert.h>
8
9#include <drivers/arm/sbsa.h>
Chandni Cherukurif3a6cab2020-09-22 18:56:25 +053010#include <plat/arm/common/plat_arm.h>
11
12#include "morello_def.h"
13
14/*
15 * Table of regions to map using the MMU.
16 * Replace or extend the below regions as required
17 */
Manoj Kumar58876122021-01-10 16:12:24 +000018#if IMAGE_BL1 || IMAGE_BL31
Chandni Cherukurif3a6cab2020-09-22 18:56:25 +053019const mmap_region_t plat_arm_mmap[] = {
20 ARM_MAP_SHARED_RAM,
21 MORELLO_MAP_DEVICE,
22 MORELLO_MAP_NS_SRAM,
23 ARM_MAP_DRAM1,
Manoj Kumarb19e62a2021-08-26 10:49:02 +053024 ARM_MAP_DRAM2,
Chandni Cherukurif3a6cab2020-09-22 18:56:25 +053025 {0}
26};
Manoj Kumar58876122021-01-10 16:12:24 +000027#endif
28#if IMAGE_BL2
29const mmap_region_t plat_arm_mmap[] = {
30 ARM_MAP_SHARED_RAM,
31 MORELLO_MAP_DEVICE,
32 MORELLO_MAP_NS_SRAM,
33 ARM_MAP_DRAM1,
34#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
35 ARM_MAP_BL1_RW,
36#endif
37 {0}
38};
39#endif
40
41#if TRUSTED_BOARD_BOOT
42int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
43{
44 assert(heap_addr != NULL);
45 assert(heap_size != NULL);
46
47 return arm_get_mbedtls_heap(heap_addr, heap_size);
48}
49#endif
50
51void plat_arm_secure_wdt_start(void)
52{
53 sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
54}
55
56void plat_arm_secure_wdt_stop(void)
57{
58 sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
59}