Stephan Gerhold | b68e4e9 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | |
| 10 | #include <msm8916_mmap.h> |
| 11 | |
| 12 | #define APCS_TCM_START_ADDR 0x10 |
| 13 | #define APCS_TCM_REDIRECT_EN_0 BIT_32(0) |
| 14 | |
| 15 | .globl plat_crash_console_init |
| 16 | .globl plat_crash_console_putc |
| 17 | .globl plat_crash_console_flush |
| 18 | .globl plat_panic_handler |
| 19 | .globl plat_my_core_pos |
| 20 | .globl plat_get_my_entrypoint |
| 21 | .globl plat_reset_handler |
| 22 | .globl platform_mem_init |
| 23 | .globl msm8916_entry_point |
| 24 | |
| 25 | /* ------------------------------------------------- |
| 26 | * int plat_crash_console_init(void) |
| 27 | * Initialize the crash console. |
| 28 | * Out: r0 - 1 on success, 0 on error |
| 29 | * Clobber list : r0 - r4 |
| 30 | * ------------------------------------------------- |
| 31 | */ |
| 32 | func plat_crash_console_init |
Stephan Gerhold | 71939dd | 2022-09-02 23:29:17 +0200 | [diff] [blame] | 33 | ldr r1, =BLSP_UART_BASE |
Stephan Gerhold | b68e4e9 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 34 | mov r0, #1 |
| 35 | b console_uartdm_core_init |
| 36 | endfunc plat_crash_console_init |
| 37 | |
| 38 | /* ------------------------------------------------- |
| 39 | * int plat_crash_console_putc(int c) |
| 40 | * Print a character on the crash console. |
| 41 | * In : r0 - character to be printed |
| 42 | * Out: r0 - printed character on success |
| 43 | * Clobber list : r1, r2 |
| 44 | * ------------------------------------------------- |
| 45 | */ |
| 46 | func plat_crash_console_putc |
Stephan Gerhold | 71939dd | 2022-09-02 23:29:17 +0200 | [diff] [blame] | 47 | ldr r1, =BLSP_UART_BASE |
Stephan Gerhold | b68e4e9 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 48 | b console_uartdm_core_putc |
| 49 | endfunc plat_crash_console_putc |
| 50 | |
| 51 | /* ------------------------------------------------- |
| 52 | * void plat_crash_console_flush(void) |
| 53 | * Force a write of all buffered data that has not |
| 54 | * been output. |
| 55 | * Clobber list : r1, r2 |
| 56 | * ------------------------------------------------- |
| 57 | */ |
| 58 | func plat_crash_console_flush |
Stephan Gerhold | 71939dd | 2022-09-02 23:29:17 +0200 | [diff] [blame] | 59 | ldr r1, =BLSP_UART_BASE |
Stephan Gerhold | b68e4e9 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 60 | b console_uartdm_core_flush |
| 61 | endfunc plat_crash_console_flush |
| 62 | |
| 63 | /* ------------------------------------------------- |
| 64 | * void plat_panic_handler(void) __dead |
| 65 | * Called when an unrecoverable error occurs. |
| 66 | * ------------------------------------------------- |
| 67 | */ |
| 68 | func plat_panic_handler |
| 69 | /* Try to shutdown/reset */ |
| 70 | ldr r0, =MPM_PS_HOLD |
| 71 | mov r1, #0 |
| 72 | str r1, [r0] |
| 73 | 1: b 1b |
| 74 | endfunc plat_panic_handler |
| 75 | |
| 76 | /* ------------------------------------------------- |
| 77 | * unsigned int plat_my_core_pos(void) |
| 78 | * Out: r0 - index of the calling CPU |
| 79 | * ------------------------------------------------- |
| 80 | */ |
| 81 | func plat_my_core_pos |
| 82 | /* There is just a single cluster so this is very simple */ |
| 83 | ldcopr r0, MPIDR |
| 84 | and r0, r0, #MPIDR_CPU_MASK |
| 85 | bx lr |
| 86 | endfunc plat_my_core_pos |
| 87 | |
| 88 | /* ------------------------------------------------- |
| 89 | * uintptr_t plat_get_my_entrypoint(void) |
| 90 | * Distinguish cold and warm boot and return warm boot |
| 91 | * entry address if available. |
| 92 | * Out: r0 - warm boot entry point or 0 on cold boot |
| 93 | * ------------------------------------------------- |
| 94 | */ |
| 95 | func plat_get_my_entrypoint |
| 96 | ldr r0, =msm8916_entry_point |
| 97 | ldr r0, [r0] |
| 98 | cmp r0, #0 |
| 99 | bxne lr |
| 100 | |
| 101 | /* |
| 102 | * Cold boot: Disable TCM redirect to L2 cache as early as |
| 103 | * possible to avoid crashes when making use of the cache. |
| 104 | */ |
| 105 | ldr r1, =APCS_CFG |
| 106 | ldr r2, [r1, #APCS_TCM_START_ADDR] |
| 107 | and r2, r2, #~APCS_TCM_REDIRECT_EN_0 |
| 108 | str r2, [r1, #APCS_TCM_START_ADDR] |
| 109 | bx lr |
| 110 | endfunc plat_get_my_entrypoint |
| 111 | |
| 112 | /* ------------------------------------------------- |
| 113 | * void platform_mem_init(void) |
| 114 | * Performs additional memory initialization early |
| 115 | * in the boot process. |
| 116 | * ------------------------------------------------- |
| 117 | */ |
| 118 | func platform_mem_init |
| 119 | /* Nothing to do here, all memory is already initialized */ |
| 120 | bx lr |
| 121 | endfunc platform_mem_init |
| 122 | |
| 123 | .data |
| 124 | .align 3 |
| 125 | |
| 126 | /* ------------------------------------------------- |
| 127 | * Warm boot entry point for CPU. Set by PSCI code. |
| 128 | * ------------------------------------------------- |
| 129 | */ |
| 130 | msm8916_entry_point: |
| 131 | .word 0 |