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Jiafei Pan46367ad2018-03-02 07:23:30 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#include <arch.h>
7#include <arch_helpers.h>
8#include <xlat_tables_v2.h>
9#include <assert.h>
10#include <debug.h>
11#include <mmio.h>
12#include "platform_def.h"
13
14const mmap_region_t *plat_ls_get_mmap(void);
15
16/*
17 * Table of memory regions for various BL stages to map using the MMU.
18 * This doesn't include Trusted SRAM as ls_setup_page_tables() already
19 * takes care of mapping it.
20 *
21 * The flash needs to be mapped as writable in order to erase the FIP's Table of
22 * Contents in case of unrecoverable error (see plat_error_handler()).
23 */
24#ifdef IMAGE_BL1
25const mmap_region_t plat_ls_mmap[] = {
26 LS_MAP_FLASH0_RW,
27 LS_MAP_NS_DRAM,
28 LS_MAP_CCSR,
29 {0}
30};
31#endif
32#ifdef IMAGE_BL2
33const mmap_region_t plat_ls_mmap[] = {
34 LS_MAP_FLASH0_RW,
35 LS_MAP_CCSR,
36 LS_MAP_NS_DRAM,
37 LS_MAP_TSP_SEC_MEM,
38 {0}
39};
40#endif
41#ifdef IMAGE_BL31
42const mmap_region_t plat_ls_mmap[] = {
43 LS_MAP_CCSR,
44 LS_MAP_FLASH0_RW,
45 LS_MAP_NS_DRAM,
46 LS_MAP_TSP_SEC_MEM,
47 {0}
48};
49#endif
50#ifdef IMAGE_BL32
51const mmap_region_t plat_ls_mmap[] = {
52 LS_MAP_CCSR,
53 LS_MAP_FLASH0_RW,
54 LS_MAP_TSP_SEC_MEM,
55 {0}
56};
57#endif
58/*
59 * Set up the page tables for the generic and platform-specific memory regions.
60 * The extents of the generic memory regions are specified by the function
61 * arguments and consist of:
62 * - Trusted SRAM seen by the BL image;
63 * - Code section;
64 * - Read-only data section;
65 * - Coherent memory region, if applicable.
66 */
67void ls_setup_page_tables(uintptr_t total_base,
68 size_t total_size,
69 uintptr_t code_start,
70 uintptr_t code_limit,
71 uintptr_t rodata_start,
72 uintptr_t rodata_limit
73#if USE_COHERENT_MEM
74 ,
75 uintptr_t coh_start,
76 uintptr_t coh_limit
77#endif
78 )
79{
80 /* Now (re-)map the platform-specific memory regions */
81 mmap_add(plat_ls_get_mmap());
82 /*
83 * Map the Trusted SRAM with appropriate memory attributes.
84 * Subsequent mappings will adjust the attributes for specific regions.
85 */
86 VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
87 (void *) total_base, (void *) (total_base + total_size));
88 mmap_add_region(total_base, total_base,
89 total_size,
90 MT_MEMORY | MT_RW | MT_SECURE);
91
92 /* Re-map the code section */
93 VERBOSE("Code region: %p - %p\n",
94 (void *) code_start, (void *) code_limit);
95 mmap_add_region(code_start, code_start,
96 code_limit - code_start,
97 MT_CODE | MT_SECURE);
98
99 /* Re-map the read-only data section */
100 VERBOSE("Read-only data region: %p - %p\n",
101 (void *) rodata_start, (void *) rodata_limit);
102 mmap_add_region(rodata_start, rodata_start,
103 rodata_limit - rodata_start,
104 MT_RO_DATA | MT_SECURE);
105
106#if USE_COHERENT_MEM
107 /* Re-map the coherent memory region */
108 VERBOSE("Coherent region: %p - %p\n",
109 (void *) coh_start, (void *) coh_limit);
110 mmap_add_region(coh_start, coh_start,
111 coh_limit - coh_start,
112 MT_DEVICE | MT_RW | MT_SECURE);
113#endif
114
115 /* Create the page tables to reflect the above mappings */
116 init_xlat_tables();
117}
118
119uintptr_t plat_get_ns_image_entrypoint(void)
120{
121#ifdef PRELOADED_BL33_BASE
122 return PRELOADED_BL33_BASE;
123#else
124 return LS_NS_DRAM_BASE;
125#endif
126}
127
128/*******************************************************************************
129 * Gets SPSR for BL32 entry
130 ******************************************************************************/
131uint32_t ls_get_spsr_for_bl32_entry(void)
132{
133 /*
134 * The Secure Payload Dispatcher service is responsible for
135 * setting the SPSR prior to entry into the BL32 image.
136 */
137 return 0;
138}
139
140/*******************************************************************************
141 * Gets SPSR for BL33 entry
142 ******************************************************************************/
143#ifndef AARCH32
144uint32_t ls_get_spsr_for_bl33_entry(void)
145{
146 unsigned int mode;
147 uint32_t spsr;
148
149 /* Figure out what mode we enter the non-secure world in */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000150 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
Jiafei Pan46367ad2018-03-02 07:23:30 +0000151
152 /*
153 * TODO: Consider the possibility of specifying the SPSR in
154 * the FIP ToC and allowing the platform to have a say as
155 * well.
156 */
157 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
158 return spsr;
159}
160#else
161/*******************************************************************************
162 * Gets SPSR for BL33 entry
163 ******************************************************************************/
164uint32_t ls_get_spsr_for_bl33_entry(void)
165{
166 unsigned int hyp_status, mode, spsr;
167
168 hyp_status = GET_VIRT_EXT(read_id_pfr1());
169
170 mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
171
172 /*
173 * TODO: Consider the possibility of specifying the SPSR in
174 * the FIP ToC and allowing the platform to have a say as
175 * well.
176 */
177 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
178 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
179 return spsr;
180}
181#endif /* AARCH32 */
182
183/*******************************************************************************
184 * Returns Layerscape platform specific memory map regions.
185 ******************************************************************************/
186const mmap_region_t *plat_ls_get_mmap(void)
187{
188 return plat_ls_mmap;
189}
190
191
192unsigned int plat_get_syscnt_freq2(void)
193{
194 unsigned int counter_base_frequency;
195
196 counter_base_frequency = COUNTER_FREQUENCY;
197
198 return counter_base_frequency;
199}