blob: b9304dcf52b322b176ff8c288b64c48511b8b316 [file] [log] [blame]
Yatharth Kochara65be2f2015-10-09 18:06:13 +01001/*
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +00002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Yatharth Kochara65be2f2015-10-09 18:06:13 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Yatharth Kochara65be2f2015-10-09 18:06:13 +01005 */
6
7#include <arch_helpers.h>
8#include <assert.h>
9#include <context.h>
10#include <context_mgmt.h>
Soby Mathewd75d2ba2016-05-17 14:01:32 +010011#include <debug.h>
Yatharth Kochara65be2f2015-10-09 18:06:13 +010012#include <platform.h>
Etienne Carriereba7c3d52017-06-07 16:41:50 +020013#include "../bl1_private.h"
Yatharth Kochara65be2f2015-10-09 18:06:13 +010014
15/*
16 * Following array will be used for context management.
17 * There are 2 instances, for the Secure and Non-Secure contexts.
18 */
19static cpu_context_t bl1_cpu_context[2];
20
21/* Following contains the cpu context pointers. */
22static void *bl1_cpu_context_ptr[2];
23
24
25void *cm_get_context(uint32_t security_state)
26{
27 assert(sec_state_is_valid(security_state));
28 return bl1_cpu_context_ptr[security_state];
29}
30
31void cm_set_context(void *context, uint32_t security_state)
32{
33 assert(sec_state_is_valid(security_state));
34 bl1_cpu_context_ptr[security_state] = context;
35}
36
37/*******************************************************************************
38 * This function prepares the context for Secure/Normal world images.
39 * Normal world images are transitioned to EL2(if supported) else EL1.
40 ******************************************************************************/
41void bl1_prepare_next_image(unsigned int image_id)
42{
43 unsigned int security_state;
44 image_desc_t *image_desc;
45 entry_point_info_t *next_bl_ep;
46
Soby Mathewd75d2ba2016-05-17 14:01:32 +010047#if CTX_INCLUDE_AARCH32_REGS
48 /*
49 * Ensure that the build flag to save AArch32 system registers in CPU
50 * context is not set for AArch64-only platforms.
51 */
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +000052 if (EL_IMPLEMENTED(1) == EL_IMPL_A64ONLY) {
Soby Mathewd75d2ba2016-05-17 14:01:32 +010053 ERROR("EL1 supports AArch64-only. Please set build flag "
54 "CTX_INCLUDE_AARCH32_REGS = 0");
55 panic();
56 }
57#endif
58
Yatharth Kochara65be2f2015-10-09 18:06:13 +010059 /* Get the image descriptor. */
60 image_desc = bl1_plat_get_image_desc(image_id);
61 assert(image_desc);
62
63 /* Get the entry point info. */
64 next_bl_ep = &image_desc->ep_info;
65
66 /* Get the image security state. */
Yatharth Kocharf11b29a2016-02-01 11:04:46 +000067 security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
Yatharth Kochara65be2f2015-10-09 18:06:13 +010068
69 /* Setup the Secure/Non-Secure context if not done already. */
70 if (!cm_get_context(security_state))
71 cm_set_context(&bl1_cpu_context[security_state], security_state);
72
73 /* Prepare the SPSR for the next BL image. */
74 if (security_state == SECURE) {
75 next_bl_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
76 DISABLE_ALL_EXCEPTIONS);
77 } else {
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +000078 /* Use EL2 if supported; else use EL1. */
79 if (EL_IMPLEMENTED(2)) {
Yatharth Kochara65be2f2015-10-09 18:06:13 +010080 next_bl_ep->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
81 DISABLE_ALL_EXCEPTIONS);
82 } else {
83 next_bl_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
84 DISABLE_ALL_EXCEPTIONS);
85 }
86 }
87
88 /* Allow platform to make change */
89 bl1_plat_set_ep_info(image_id, next_bl_ep);
90
91 /* Prepare the context for the next BL image. */
92 cm_init_my_context(next_bl_ep);
93 cm_prepare_el3_exit(security_state);
94
95 /* Indicate that image is in execution state. */
96 image_desc->state = IMAGE_STATE_EXECUTED;
97
98 print_entry_point_info(next_bl_ep);
99}