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Louis Mayencourtf57f1082019-05-14 11:00:45 +01001/*
johpow019131eb82020-10-06 17:55:25 -05002 * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
Louis Mayencourtf57f1082019-05-14 11:00:45 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Jimmy Brisson3571fb92020-06-01 10:18:22 -05007#ifndef CORTEX_A78_H
8#define CORTEX_A78_H
Louis Mayencourtf57f1082019-05-14 11:00:45 +01009
10#include <lib/utils_def.h>
11
Jimmy Brisson3571fb92020-06-01 10:18:22 -050012#define CORTEX_A78_MIDR U(0x410FD410)
Louis Mayencourtf57f1082019-05-14 11:00:45 +010013
14/*******************************************************************************
15 * CPU Extended Control register specific definitions.
16 ******************************************************************************/
Jimmy Brisson3571fb92020-06-01 10:18:22 -050017#define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4
johpow019131eb82020-10-06 17:55:25 -050018#define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
nayanpatel-arm39e08652021-09-28 17:31:50 -070019#define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
20#define CPUECTLR_EL1_PF_MODE_LSB U(6)
21#define CPUECTLR_EL1_PF_MODE_WIDTH U(2)
Louis Mayencourtf57f1082019-05-14 11:00:45 +010022
23/*******************************************************************************
24 * CPU Power Control register specific definitions
25 ******************************************************************************/
johpow019131eb82020-10-06 17:55:25 -050026#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7
Jimmy Brisson3571fb92020-06-01 10:18:22 -050027#define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
Louis Mayencourtf57f1082019-05-14 11:00:45 +010028
Balint Dobszaydb2ec852019-07-15 11:46:20 +020029/*******************************************************************************
30 * CPU Auxiliary Control register specific definitions.
31 ******************************************************************************/
johpow019131eb82020-10-06 17:55:25 -050032#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
Balint Dobszaydb2ec852019-07-15 11:46:20 +020033
Jimmy Brisson3571fb92020-06-01 10:18:22 -050034#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
35#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
johpow01b3e82942021-04-30 18:08:52 -050036#define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
Madhukar Pappireddy4efede72019-12-18 15:56:27 -060037
Balint Dobszaydb2ec852019-07-15 11:46:20 +020038/*******************************************************************************
39 * CPU Activity Monitor Unit register specific definitions.
40 ******************************************************************************/
johpow019131eb82020-10-06 17:55:25 -050041#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
42#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
43#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
44#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
Balint Dobszaydb2ec852019-07-15 11:46:20 +020045
johpow019131eb82020-10-06 17:55:25 -050046#define CORTEX_A78_AMU_GROUP0_MASK U(0xF)
47#define CORTEX_A78_AMU_GROUP1_MASK U(0x7)
Balint Dobszaydb2ec852019-07-15 11:46:20 +020048
Jimmy Brisson3571fb92020-06-01 10:18:22 -050049#endif /* CORTEX_A78_H */