blob: 2c55cb06d3c2ef9610a979340d7130f7266697d5 [file] [log] [blame]
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +02001#
2# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7ifeq (${RCAR_LSI},${RCAR_AUTO})
8 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
9 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
10 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
11 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
Valentine Barshakf2184142018-10-30 02:06:17 +030012 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/V3M/pfc_init_v3m.c
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +020013
14else ifdef RCAR_LSI_CUT_COMPAT
15 ifeq (${RCAR_LSI},${RCAR_H3})
16 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
17 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
18 endif
19 ifeq (${RCAR_LSI},${RCAR_H3N})
20 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
21 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
22 endif
23 ifeq (${RCAR_LSI},${RCAR_M3})
24 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
25 endif
26 ifeq (${RCAR_LSI},${RCAR_M3N})
27 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
28 endif
Valentine Barshakf2184142018-10-30 02:06:17 +030029 ifeq (${RCAR_LSI},${RCAR_V3M})
30 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/V3M/pfc_init_v3m.c
31 endif
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +020032 ifeq (${RCAR_LSI},${RCAR_E3})
33 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
34 endif
Marek Vasut6f4984c2018-06-14 06:26:45 +020035 ifeq (${RCAR_LSI},${RCAR_D3})
36 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c
37 endif
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +020038else
39 ifeq (${RCAR_LSI},${RCAR_H3})
40 ifeq (${LSI_CUT},10)
41 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
42 else ifeq (${LSI_CUT},11)
43 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
44 else
45# LSI_CUT 20 or later
46 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
47 endif
48 endif
49 ifeq (${RCAR_LSI},${RCAR_H3N})
50 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
51 endif
52 ifeq (${RCAR_LSI},${RCAR_M3})
53 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
54 endif
55 ifeq (${RCAR_LSI},${RCAR_M3N})
56 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
57 endif
Valentine Barshakf2184142018-10-30 02:06:17 +030058 ifeq (${RCAR_LSI},${RCAR_V3M})
59 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/V3M/pfc_init_v3m.c
60 endif
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +020061 ifeq (${RCAR_LSI},${RCAR_E3})
62 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
63 endif
Marek Vasut6f4984c2018-06-14 06:26:45 +020064 ifeq (${RCAR_LSI},${RCAR_D3})
65 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c
66 endif
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +020067endif
68
69BL2_SOURCES += drivers/staging/renesas/rcar/pfc/pfc_init.c