Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 1 | /* |
Sieu Mun Tang | a544da1 | 2022-02-28 15:24:59 +0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 3 | * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. |
Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #ifndef PLAT_SOCFPGA_DEF_H |
| 9 | #define PLAT_SOCFPGA_DEF_H |
| 10 | |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 11 | #include "agilex_system_manager.h" |
Sieu Mun Tang | 6e0e1b5 | 2023-12-22 11:30:46 +0800 | [diff] [blame] | 12 | #include <lib/utils_def.h> |
Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 13 | #include <platform_def.h> |
| 14 | |
| 15 | /* Platform Setting */ |
Sieu Mun Tang | 334ea37 | 2023-12-22 00:43:57 +0800 | [diff] [blame] | 16 | #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX |
| 17 | #define BOOT_SOURCE BOOT_SOURCE_SDMMC |
| 18 | #define PLAT_PRIMARY_CPU 0 |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 19 | #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT |
Sieu Mun Tang | 334ea37 | 2023-12-22 00:43:57 +0800 | [diff] [blame] | 20 | #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT |
Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 21 | |
Sieu Mun Tang | a544da1 | 2022-02-28 15:24:59 +0800 | [diff] [blame] | 22 | /* FPGA config helpers */ |
| 23 | #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 |
| 24 | #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000 |
| 25 | |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 26 | /* QSPI Setting */ |
| 27 | #define CAD_QSPIDATA_OFST 0xff900000 |
| 28 | #define CAD_QSPI_OFFSET 0xff8d2000 |
| 29 | |
Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 30 | /* Register Mapping */ |
Abdul Halim, Muhammad Hadi Asyrafi | 616b5e7 | 2020-08-05 22:12:23 +0800 | [diff] [blame] | 31 | #define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000 |
Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 32 | #define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000) |
Abdul Halim, Muhammad Hadi Asyrafi | 616b5e7 | 2020-08-05 22:12:23 +0800 | [diff] [blame] | 33 | |
Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 34 | #define SOCFPGA_MMC_REG_BASE 0xff808000 |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 35 | #define SOCFPGA_MEMCTRL_REG_BASE 0xf8011100 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 36 | #define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 |
Hadi Asyrafi | 8ebd237 | 2019-12-23 17:58:04 +0800 | [diff] [blame] | 37 | #define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 |
Sieu Mun Tang | 334ea37 | 2023-12-22 00:43:57 +0800 | [diff] [blame] | 38 | #define SOCFPGA_ECC_QSPI_REG_BASE 0xffa22000 |
Hadi Asyrafi | 8ebd237 | 2019-12-23 17:58:04 +0800 | [diff] [blame] | 39 | |
| 40 | #define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000 |
| 41 | #define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 |
| 42 | #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200 |
| 43 | #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 |
Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 44 | |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 45 | /******************************************************************************* |
| 46 | * Platform memory map related constants |
| 47 | ******************************************************************************/ |
| 48 | #define DRAM_BASE (0x0) |
| 49 | #define DRAM_SIZE (0x80000000) |
| 50 | |
| 51 | #define OCRAM_BASE (0xFFE00000) |
| 52 | #define OCRAM_SIZE (0x00040000) |
| 53 | |
| 54 | #define MEM64_BASE (0x0100000000) |
| 55 | #define MEM64_SIZE (0x1F00000000) |
| 56 | |
| 57 | #define DEVICE1_BASE (0x80000000) |
| 58 | #define DEVICE1_SIZE (0x60000000) |
| 59 | |
| 60 | #define DEVICE2_BASE (0xF7000000) |
| 61 | #define DEVICE2_SIZE (0x08E00000) |
| 62 | |
| 63 | #define DEVICE3_BASE (0xFFFC0000) |
| 64 | #define DEVICE3_SIZE (0x00008000) |
| 65 | |
| 66 | #define DEVICE4_BASE (0x2000000000) |
| 67 | #define DEVICE4_SIZE (0x0100000000) |
| 68 | |
Sieu Mun Tang | 334ea37 | 2023-12-22 00:43:57 +0800 | [diff] [blame] | 69 | #define BL2_BASE (0xffe00000) |
| 70 | #define BL2_LIMIT (0xffe2b000) |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 71 | |
Sieu Mun Tang | 334ea37 | 2023-12-22 00:43:57 +0800 | [diff] [blame] | 72 | #define BL31_BASE (0x1000) |
| 73 | #define BL31_LIMIT (0x81000) |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 74 | |
| 75 | /******************************************************************************* |
| 76 | * UART related constants |
| 77 | ******************************************************************************/ |
Sieu Mun Tang | 334ea37 | 2023-12-22 00:43:57 +0800 | [diff] [blame] | 78 | #define PLAT_UART0_BASE (0xFFC02000) |
| 79 | #define PLAT_UART1_BASE (0xFFC02100) |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 80 | |
| 81 | /******************************************************************************* |
Sieu Mun Tang | 6284537 | 2023-06-09 23:33:36 +0800 | [diff] [blame] | 82 | * WDT related constants |
| 83 | ******************************************************************************/ |
| 84 | #define WDT_BASE (0xFFD00200) |
| 85 | |
| 86 | /******************************************************************************* |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 87 | * GIC related constants |
| 88 | ******************************************************************************/ |
Sieu Mun Tang | 334ea37 | 2023-12-22 00:43:57 +0800 | [diff] [blame] | 89 | #define PLAT_GIC_BASE (0xFFFC0000) |
| 90 | #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) |
| 91 | #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) |
| 92 | #define PLAT_GICR_BASE 0 |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 93 | |
Sieu Mun Tang | 6e0e1b5 | 2023-12-22 11:30:46 +0800 | [diff] [blame] | 94 | #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) |
| 95 | #define PLAT_HZ_CONVERT_TO_MHZ (1000000) |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 96 | |
Jit Loon Lim | 4c249f1 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 97 | /******************************************************************************* |
| 98 | * SDMMC related pointer function |
| 99 | ******************************************************************************/ |
Sieu Mun Tang | 334ea37 | 2023-12-22 00:43:57 +0800 | [diff] [blame] | 100 | #define SDMMC_READ_BLOCKS mmc_read_blocks |
| 101 | #define SDMMC_WRITE_BLOCKS mmc_write_blocks |
Jit Loon Lim | 4c249f1 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 102 | |
| 103 | /******************************************************************************* |
| 104 | * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset |
| 105 | * is done and HPS should trigger warm reset via RMR_EL3. |
| 106 | ******************************************************************************/ |
| 107 | #define L2_RESET_DONE_REG 0xFFD12218 |
| 108 | |
BenjaminLimJL | a4a4327 | 2022-04-06 10:19:16 +0800 | [diff] [blame] | 109 | /* Platform specific system counter */ |
Sieu Mun Tang | 6e0e1b5 | 2023-12-22 11:30:46 +0800 | [diff] [blame] | 110 | #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400) |
Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 111 | |
BenjaminLimJL | a4a4327 | 2022-04-06 10:19:16 +0800 | [diff] [blame] | 112 | #endif /* PLAT_SOCFPGA_DEF_H */ |