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Jeenu Viswambharand1ff62a2018-01-31 10:57:46 +00001/*
Balint Dobszay5ce2c322020-01-10 17:16:27 +01002 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
Jeenu Viswambharand1ff62a2018-01-31 10:57:46 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8
Madhukar Pappireddy862c4b82020-02-13 15:36:50 -06009#include "fvp-base-gicv3-psci-dynamiq-common.dtsi"
Jeenu Viswambharand1ff62a2018-01-31 10:57:46 +000010
11&CPU0 {
12 reg = <0x0 0x0>;
13};
14
15&CPU1 {
16 reg = <0x0 0x100>;
17};
18
19&CPU2 {
20 reg = <0x0 0x200>;
21};
22
23&CPU3 {
24 reg = <0x0 0x300>;
25};
26
27&CPU4 {
28 reg = <0x0 0x400>;
29};
30
31&CPU5 {
32 reg = <0x0 0x500>;
33};
34
35&CPU6 {
36 reg = <0x0 0x600>;
37};
38
39&CPU7 {
40 reg = <0x0 0x700>;
41};