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Haojian Zhuang934ae712017-05-24 08:47:49 +08001/*
Haojian Zhuang3bd94382018-01-28 23:33:02 +08002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Haojian Zhuang934ae712017-05-24 08:47:49 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
8#include <assert.h>
9#include <bl_common.h>
10#include <console.h>
11#include <debug.h>
Victor Chong2d9a42d2017-08-17 15:21:10 +090012#include <desc_image_load.h>
Haojian Zhuang934ae712017-05-24 08:47:49 +080013#include <dw_mmc.h>
14#include <emmc.h>
15#include <errno.h>
16#include <hi6220.h>
17#include <hisi_mcu.h>
18#include <hisi_sram_map.h>
19#include <mmio.h>
Victor Chong7d787f52017-08-16 13:53:56 +090020#ifdef SPD_opteed
21#include <optee_utils.h>
22#endif
Haojian Zhuangb755da32018-01-25 16:10:14 +080023#include <platform.h>
Michael Brandlafdff3c2018-02-22 16:30:30 +010024#include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/
Haojian Zhuang934ae712017-05-24 08:47:49 +080025#include <string.h>
26
Haojian Zhuang934ae712017-05-24 08:47:49 +080027#include "hikey_private.h"
28
29/*
30 * The next 2 constants identify the extents of the code & RO data region.
31 * These addresses are used by the MMU setup code and therefore they must be
32 * page-aligned. It is the responsibility of the linker script to ensure that
33 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
34 */
35#define BL2_RO_BASE (unsigned long)(&__RO_START__)
36#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
37
Haojian Zhuangb755da32018-01-25 16:10:14 +080038#define BL2_RW_BASE (BL2_RO_LIMIT)
39
Haojian Zhuang934ae712017-05-24 08:47:49 +080040/*
41 * The next 2 constants identify the extents of the coherent memory region.
42 * These addresses are used by the MMU setup code and therefore they must be
43 * page-aligned. It is the responsibility of the linker script to ensure that
44 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
45 * page-aligned addresses.
46 */
47#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
48#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
49
Haojian Zhuangb755da32018-01-25 16:10:14 +080050static meminfo_t bl2_el3_tzram_layout;
51
52enum {
53 BOOT_MODE_RECOVERY = 0,
54 BOOT_MODE_NORMAL,
55 BOOT_MODE_MASK = 1,
56};
Haojian Zhuang934ae712017-05-24 08:47:49 +080057
Victor Chong2d9a42d2017-08-17 15:21:10 +090058/*******************************************************************************
59 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
60 * Return 0 on success, -1 otherwise.
61 ******************************************************************************/
Victor Chong2d9a42d2017-08-17 15:21:10 +090062int plat_hikey_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
Haojian Zhuang934ae712017-05-24 08:47:49 +080063{
64 /* Enable MCU SRAM */
65 hisi_mcu_enable_sram();
66
67 /* Load MCU binary into SRAM */
68 hisi_mcu_load_image(scp_bl2_image_info->image_base,
69 scp_bl2_image_info->image_size);
70 /* Let MCU running */
71 hisi_mcu_start_run();
72
73 INFO("%s: MCU PC is at 0x%x\n",
74 __func__, mmio_read_32(AO_SC_MCU_SUBSYS_STAT2));
75 INFO("%s: AO_SC_PERIPH_CLKSTAT4 is 0x%x\n",
76 __func__, mmio_read_32(AO_SC_PERIPH_CLKSTAT4));
77 return 0;
78}
79
Victor Chong2d9a42d2017-08-17 15:21:10 +090080/*******************************************************************************
81 * Gets SPSR for BL32 entry
82 ******************************************************************************/
83uint32_t hikey_get_spsr_for_bl32_entry(void)
84{
85 /*
86 * The Secure Payload Dispatcher service is responsible for
87 * setting the SPSR prior to entry into the BL3-2 image.
88 */
89 return 0;
90}
91
92/*******************************************************************************
93 * Gets SPSR for BL33 entry
94 ******************************************************************************/
95#ifndef AARCH32
96uint32_t hikey_get_spsr_for_bl33_entry(void)
97{
98 unsigned int mode;
99 uint32_t spsr;
100
101 /* Figure out what mode we enter the non-secure world in */
102 mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
103
104 /*
105 * TODO: Consider the possibility of specifying the SPSR in
106 * the FIP ToC and allowing the platform to have a say as
107 * well.
108 */
109 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
110 return spsr;
111}
112#else
113uint32_t hikey_get_spsr_for_bl33_entry(void)
114{
115 unsigned int hyp_status, mode, spsr;
116
117 hyp_status = GET_VIRT_EXT(read_id_pfr1());
118
119 mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
120
121 /*
122 * TODO: Consider the possibility of specifying the SPSR in
123 * the FIP ToC and allowing the platform to have a say as
124 * well.
125 */
126 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
127 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
128 return spsr;
129}
130#endif /* AARCH32 */
131
Victor Chong2d9a42d2017-08-17 15:21:10 +0900132int hikey_bl2_handle_post_image_load(unsigned int image_id)
133{
134 int err = 0;
135 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Victor Chong7d787f52017-08-16 13:53:56 +0900136#ifdef SPD_opteed
137 bl_mem_params_node_t *pager_mem_params = NULL;
138 bl_mem_params_node_t *paged_mem_params = NULL;
139#endif
Victor Chong2d9a42d2017-08-17 15:21:10 +0900140 assert(bl_mem_params);
141
142 switch (image_id) {
143#ifdef AARCH64
144 case BL32_IMAGE_ID:
Victor Chong7d787f52017-08-16 13:53:56 +0900145#ifdef SPD_opteed
146 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
147 assert(pager_mem_params);
148
149 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
150 assert(paged_mem_params);
151
152 err = parse_optee_header(&bl_mem_params->ep_info,
153 &pager_mem_params->image_info,
154 &paged_mem_params->image_info);
155 if (err != 0) {
156 WARN("OPTEE header parse error.\n");
157 }
158#endif
Victor Chong2d9a42d2017-08-17 15:21:10 +0900159 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl32_entry();
160 break;
161#endif
162
163 case BL33_IMAGE_ID:
164 /* BL33 expects to receive the primary CPU MPID (through r0) */
165 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
166 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl33_entry();
167 break;
168
169#ifdef SCP_BL2_BASE
170 case SCP_BL2_IMAGE_ID:
171 /* The subsequent handling of SCP_BL2 is platform specific */
172 err = plat_hikey_bl2_handle_scp_bl2(&bl_mem_params->image_info);
173 if (err) {
174 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
175 }
176 break;
177#endif
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000178 default:
179 /* Do nothing in default case */
180 break;
Victor Chong2d9a42d2017-08-17 15:21:10 +0900181 }
182
183 return err;
184}
185
186/*******************************************************************************
187 * This function can be used by the platforms to update/use image
188 * information for given `image_id`.
189 ******************************************************************************/
190int bl2_plat_handle_post_image_load(unsigned int image_id)
191{
192 return hikey_bl2_handle_post_image_load(image_id);
193}
Haojian Zhuang934ae712017-05-24 08:47:49 +0800194
195static void reset_dwmmc_clk(void)
196{
197 unsigned int data;
198
199 /* disable mmc0 bus clock */
200 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0);
201 do {
202 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
203 } while (data & PERI_CLK0_MMC0);
204 /* enable mmc0 bus clock */
205 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0);
206 do {
207 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
208 } while (!(data & PERI_CLK0_MMC0));
209 /* reset mmc0 clock domain */
210 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0);
211
212 /* bypass mmc0 clock phase */
213 data = mmio_read_32(PERI_SC_PERIPH_CTRL2);
214 data |= 3;
215 mmio_write_32(PERI_SC_PERIPH_CTRL2, data);
216
217 /* disable low power */
218 data = mmio_read_32(PERI_SC_PERIPH_CTRL13);
219 data |= 1 << 3;
220 mmio_write_32(PERI_SC_PERIPH_CTRL13, data);
221 do {
222 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
223 } while (!(data & PERI_RST0_MMC0));
224
225 /* unreset mmc0 clock domain */
226 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0);
227 do {
228 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
229 } while (data & PERI_RST0_MMC0);
230}
231
232static void hikey_boardid_init(void)
233{
234 u_register_t midr;
235
236 midr = read_midr();
237 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr);
238 INFO("[BDID] [%x] midr: 0x%x\n", MEMORY_AXI_CHIP_ADDR,
239 (unsigned int)midr);
240
241 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0);
242 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b);
243
244 mmio_write_32(ACPU_ARM64_FLAGA, 0x1234);
245 mmio_write_32(ACPU_ARM64_FLAGB, 0x5678);
246}
247
248static void hikey_sd_init(void)
249{
250 /* switch pinmux to SD */
251 mmio_write_32(IOMG_SD_CLK, IOMG_MUX_FUNC0);
252 mmio_write_32(IOMG_SD_CMD, IOMG_MUX_FUNC0);
253 mmio_write_32(IOMG_SD_DATA0, IOMG_MUX_FUNC0);
254 mmio_write_32(IOMG_SD_DATA1, IOMG_MUX_FUNC0);
255 mmio_write_32(IOMG_SD_DATA2, IOMG_MUX_FUNC0);
256 mmio_write_32(IOMG_SD_DATA3, IOMG_MUX_FUNC0);
257
258 mmio_write_32(IOCG_SD_CLK, IOCG_INPUT_16MA);
259 mmio_write_32(IOCG_SD_CMD, IOCG_INPUT_12MA);
260 mmio_write_32(IOCG_SD_DATA0, IOCG_INPUT_12MA);
261 mmio_write_32(IOCG_SD_DATA1, IOCG_INPUT_12MA);
262 mmio_write_32(IOCG_SD_DATA2, IOCG_INPUT_12MA);
263 mmio_write_32(IOCG_SD_DATA3, IOCG_INPUT_12MA);
264
265 /* set SD Card detect as nopull */
266 mmio_write_32(IOCG_GPIO8, 0);
267}
268
269static void hikey_jumper_init(void)
270{
271 /* set jumper detect as nopull */
272 mmio_write_32(IOCG_GPIO24, 0);
273 /* set jumper detect as GPIO */
274 mmio_write_32(IOMG_GPIO24, IOMG_MUX_FUNC0);
275}
276
Haojian Zhuangb755da32018-01-25 16:10:14 +0800277void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
278 u_register_t arg3, u_register_t arg4)
279{
Haojian Zhuang934ae712017-05-24 08:47:49 +0800280 /* Initialize the console to provide early debug support */
281 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
Haojian Zhuangb755da32018-01-25 16:10:14 +0800282 /*
283 * Allow BL2 to see the whole Trusted RAM.
284 */
285 bl2_el3_tzram_layout.total_base = BL2_RW_BASE;
286 bl2_el3_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE;
287}
Haojian Zhuang934ae712017-05-24 08:47:49 +0800288
Haojian Zhuangb755da32018-01-25 16:10:14 +0800289void bl2_el3_plat_arch_setup(void)
290{
291 hikey_init_mmu_el3(bl2_el3_tzram_layout.total_base,
292 bl2_el3_tzram_layout.total_size,
293 BL2_RO_BASE,
294 BL2_RO_LIMIT,
295 BL2_COHERENT_RAM_BASE,
296 BL2_COHERENT_RAM_LIMIT);
297}
Haojian Zhuang934ae712017-05-24 08:47:49 +0800298
Haojian Zhuangb755da32018-01-25 16:10:14 +0800299void bl2_platform_setup(void)
300{
301 dw_mmc_params_t params;
Haojian Zhuang934ae712017-05-24 08:47:49 +0800302
Haojian Zhuangb755da32018-01-25 16:10:14 +0800303 hikey_sp804_init();
304 hikey_gpio_init();
305 hikey_pmussi_init();
306 hikey_hi6553_init();
Haojian Zhuanga403c3a2018-04-11 19:06:14 +0800307 /* Clear SRAM since it'll be used by MCU right now. */
308 memset((void *)SRAM_BASE, 0, SRAM_SIZE);
Haojian Zhuangb755da32018-01-25 16:10:14 +0800309
Haojian Zhuang934ae712017-05-24 08:47:49 +0800310 dsb();
Haojian Zhuange18de672018-04-11 19:05:32 +0800311 hikey_ddr_init(DDR_FREQ_800M);
Haojian Zhuangb755da32018-01-25 16:10:14 +0800312 hikey_security_setup();
313
Haojian Zhuang934ae712017-05-24 08:47:49 +0800314 hikey_boardid_init();
315 init_acpu_dvfs();
Haojian Zhuangb755da32018-01-25 16:10:14 +0800316 hikey_rtc_init();
Haojian Zhuang934ae712017-05-24 08:47:49 +0800317 hikey_sd_init();
318 hikey_jumper_init();
319
Haojian Zhuangb755da32018-01-25 16:10:14 +0800320 hikey_mmc_pll_init();
321
Haojian Zhuanga403c3a2018-04-11 19:06:14 +0800322 /* Clean SRAM before MCU used */
323 clean_dcache_range(SRAM_BASE, SRAM_SIZE);
324
Haojian Zhuang934ae712017-05-24 08:47:49 +0800325 reset_dwmmc_clk();
326 memset(&params, 0, sizeof(dw_mmc_params_t));
327 params.reg_base = DWMMC0_BASE;
328 params.desc_base = HIKEY_MMC_DESC_BASE;
329 params.desc_size = 1 << 20;
330 params.clk_rate = 24 * 1000 * 1000;
331 params.bus_width = EMMC_BUS_WIDTH_8;
332 params.flags = EMMC_FLAG_CMD23;
333 dw_mmc_init(&params);
334
335 hikey_io_setup();
336}