Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __PLATFORM_DEF_H__ |
| 32 | #define __PLATFORM_DEF_H__ |
| 33 | |
| 34 | #include <arch.h> |
| 35 | #include "../zynqmp_def.h" |
| 36 | |
| 37 | /******************************************************************************* |
| 38 | * Generic platform constants |
| 39 | ******************************************************************************/ |
| 40 | |
| 41 | /* Size of cacheable stacks */ |
| 42 | #define PLATFORM_STACK_SIZE 0x440 |
| 43 | |
| 44 | #define PLATFORM_CORE_COUNT 4 |
| 45 | #define PLAT_NUM_POWER_DOMAINS 5 |
| 46 | #define PLAT_MAX_PWR_LVL 1 |
| 47 | #define PLAT_MAX_RET_STATE 1 |
| 48 | #define PLAT_MAX_OFF_STATE 2 |
| 49 | |
| 50 | /******************************************************************************* |
| 51 | * BL31 specific defines. |
| 52 | ******************************************************************************/ |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 53 | /* |
| 54 | * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if |
| 55 | * present). BL31_BASE is calculated using the current BL31 debug size plus a |
| 56 | * little space for growth. |
| 57 | */ |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 58 | #ifndef ZYNQMP_ATF_MEM_BASE |
| 59 | # define BL31_BASE 0xfffe5000 |
| 60 | # define BL31_PROGBITS_LIMIT 0xffffa000 |
| 61 | # define BL31_LIMIT 0xffffffff |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 62 | #else |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 63 | # define BL31_BASE (ZYNQMP_ATF_MEM_BASE) |
| 64 | # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1) |
| 65 | # ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE |
| 66 | # define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1) |
| 67 | # endif |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 68 | #endif |
| 69 | |
| 70 | /******************************************************************************* |
| 71 | * BL32 specific defines. |
| 72 | ******************************************************************************/ |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 73 | #ifndef ZYNQMP_BL32_MEM_BASE |
| 74 | # define BL32_BASE 0x60000000 |
| 75 | # define BL32_LIMIT 0x7fffffff |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 76 | #else |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 77 | # define BL32_BASE (ZYNQMP_BL32_MEM_BASE) |
| 78 | # define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 79 | #endif |
| 80 | |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 81 | /******************************************************************************* |
| 82 | * BL33 specific defines. |
| 83 | ******************************************************************************/ |
| 84 | #ifndef PRELOADED_BL33_BASE |
| 85 | # define PLAT_ARM_NS_IMAGE_OFFSET 0x8000000 |
| 86 | #else |
| 87 | # define PLAT_ARM_NS_IMAGE_OFFSET PRELOADED_BL33_BASE |
| 88 | #endif |
| 89 | |
| 90 | /******************************************************************************* |
| 91 | * TSP specific defines. |
| 92 | ******************************************************************************/ |
| 93 | #define TSP_SEC_MEM_BASE BL32_BASE |
| 94 | #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) |
| 95 | |
| 96 | /* ID of the secure physical generic timer interrupt used by the TSP */ |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 97 | #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER |
| 98 | |
| 99 | /******************************************************************************* |
| 100 | * Platform specific page table and MMU setup constants |
| 101 | ******************************************************************************/ |
| 102 | #define ADDR_SPACE_SIZE (1ull << 32) |
Soren Brinkmann | 845cd5c | 2016-04-22 10:02:46 -0700 | [diff] [blame^] | 103 | #define MAX_MMAP_REGIONS 6 |
| 104 | #if IMAGE_BL32 |
| 105 | # define MAX_XLAT_TABLES 5 |
| 106 | #else |
| 107 | # define MAX_XLAT_TABLES 4 |
| 108 | #endif |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 109 | |
| 110 | #define CACHE_WRITEBACK_SHIFT 6 |
| 111 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 112 | |
| 113 | #define PLAT_ARM_GICD_BASE BASE_GICD_BASE |
| 114 | #define PLAT_ARM_GICC_BASE BASE_GICC_BASE |
| 115 | /* |
| 116 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 117 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 118 | * as Group 0 interrupts. |
| 119 | */ |
| 120 | #define PLAT_ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ |
| 121 | IRQ_SEC_IPI_APU, \ |
| 122 | ARM_IRQ_SEC_SGI_0, \ |
| 123 | ARM_IRQ_SEC_SGI_1, \ |
| 124 | ARM_IRQ_SEC_SGI_2, \ |
| 125 | ARM_IRQ_SEC_SGI_3, \ |
| 126 | ARM_IRQ_SEC_SGI_4, \ |
| 127 | ARM_IRQ_SEC_SGI_5, \ |
| 128 | ARM_IRQ_SEC_SGI_6, \ |
| 129 | ARM_IRQ_SEC_SGI_7 |
| 130 | |
| 131 | #define PLAT_ARM_G0_IRQS |
| 132 | |
| 133 | #endif /* __PLATFORM_DEF_H__ */ |