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Jens Wiklander52c798e2015-12-07 14:37:10 +01001/*
Hongbo Zhang32338ec2018-04-19 13:06:07 +08002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Jens Wiklander52c798e2015-12-07 14:37:10 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Jens Wiklander52c798e2015-12-07 14:37:10 +01005 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Jens Wiklander52c798e2015-12-07 14:37:10 +01009
10#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/tbbr/tbbr_img_def.h>
12#include <lib/utils_def.h>
13#include <plat/common/common_def.h>
Jens Wiklander52c798e2015-12-07 14:37:10 +010014
15/* Special value used to verify platform parameters from BL2 to BL3-1 */
16#define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
17
18#define PLATFORM_STACK_SIZE 0x1000
19
Etienne Carriere911de8c2018-02-02 13:23:22 +010020#if ARM_ARCH_MAJOR == 7
21#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
22#define PLATFORM_CLUSTER_COUNT 1
23#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
24#define PLATFORM_CLUSTER1_CORE_COUNT 0
25#else
Jens Wiklander52c798e2015-12-07 14:37:10 +010026#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
27#define PLATFORM_CLUSTER_COUNT 2
28#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
29#define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
Etienne Carriere911de8c2018-02-02 13:23:22 +010030#endif
Jens Wiklander52c798e2015-12-07 14:37:10 +010031#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
32 PLATFORM_CLUSTER1_CORE_COUNT)
33
34#define QEMU_PRIMARY_CPU 0
35
36#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
37 PLATFORM_CORE_COUNT)
38#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
39
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010040#define PLAT_MAX_RET_STATE U(1)
41#define PLAT_MAX_OFF_STATE U(2)
Jens Wiklander52c798e2015-12-07 14:37:10 +010042
43/* Local power state for power domains in Run state. */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010044#define PLAT_LOCAL_STATE_RUN U(0)
Jens Wiklander52c798e2015-12-07 14:37:10 +010045/* Local power state for retention. Valid only for CPU power domains */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010046#define PLAT_LOCAL_STATE_RET U(1)
Jens Wiklander52c798e2015-12-07 14:37:10 +010047/*
48 * Local power state for OFF/power-down. Valid for CPU and cluster power
49 * domains.
50 */
51#define PLAT_LOCAL_STATE_OFF 2
52
53/*
54 * Macros used to parse state information from State-ID if it is using the
55 * recommended encoding for State-ID.
56 */
57#define PLAT_LOCAL_PSTATE_WIDTH 4
58#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
59
60/*
61 * Some data must be aligned on the biggest cache line size in the platform.
62 * This is known only to the platform as it might have a combination of
63 * integrated and external caches.
64 */
65#define CACHE_WRITEBACK_SHIFT 6
66#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
67
68/*
69 * Partition memory into secure ROM, non-secure DRAM, secure "SRAM",
70 * and secure DRAM.
71 */
72#define SEC_ROM_BASE 0x00000000
73#define SEC_ROM_SIZE 0x00020000
74
75#define NS_DRAM0_BASE 0x40000000
76#define NS_DRAM0_SIZE 0x3de00000
77
78#define SEC_SRAM_BASE 0x0e000000
Michalis Pappase4c00bb2018-03-20 14:30:00 +080079#define SEC_SRAM_SIZE 0x00060000
Jens Wiklander52c798e2015-12-07 14:37:10 +010080
81#define SEC_DRAM_BASE 0x0e100000
82#define SEC_DRAM_SIZE 0x00f00000
83
Etienne Carriere2ddec182017-10-26 12:05:01 +020084/* Load pageable part of OP-TEE 2MB above secure DRAM base */
85#define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000)
Jens Wiklander0acbaaa2017-08-24 13:16:26 +020086#define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000
87
Jens Wiklander52c798e2015-12-07 14:37:10 +010088/*
89 * ARM-TF lives in SRAM, partition it here
90 */
91
92#define SHARED_RAM_BASE SEC_SRAM_BASE
93#define SHARED_RAM_SIZE 0x00001000
94
95#define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE
96#define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE)
97#define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8)
98#define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \
99 PLAT_QEMU_HOLD_ENTRY_SIZE)
Etienne Carriere5eb85e42017-10-24 01:09:52 +0200100#define PLAT_QEMU_HOLD_ENTRY_SHIFT 3
101#define PLAT_QEMU_HOLD_ENTRY_SIZE (1 << PLAT_QEMU_HOLD_ENTRY_SHIFT)
Jens Wiklander52c798e2015-12-07 14:37:10 +0100102#define PLAT_QEMU_HOLD_STATE_WAIT 0
103#define PLAT_QEMU_HOLD_STATE_GO 1
104
105#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE)
106#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
107
108/*
109 * BL1 specific defines.
110 *
111 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
112 * addresses.
113 * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using
114 * the current BL1 RW debug size plus a little space for growth.
115 */
116#define BL1_RO_BASE SEC_ROM_BASE
117#define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE)
118#define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000)
119#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
120
121/*
122 * BL2 specific defines.
123 *
124 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
125 * size plus a little space for growth.
126 */
Michalis Pappase4c00bb2018-03-20 14:30:00 +0800127#define BL2_BASE (BL31_BASE - 0x25000)
Jens Wiklander52c798e2015-12-07 14:37:10 +0100128#define BL2_LIMIT BL31_BASE
129
130/*
131 * BL3-1 specific defines.
132 *
133 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
134 * current BL3-1 debug size plus a little space for growth.
135 */
136#define BL31_BASE (BL31_LIMIT - 0x20000)
137#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
138#define BL31_PROGBITS_LIMIT BL1_RW_BASE
139
140
141/*
142 * BL3-2 specific defines.
143 *
144 * BL3-2 can execute from Secure SRAM, or Secure DRAM.
145 */
146#define BL32_SRAM_BASE BL_RAM_BASE
147#define BL32_SRAM_LIMIT BL31_BASE
148#define BL32_DRAM_BASE SEC_DRAM_BASE
149#define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE)
150
151#define SEC_SRAM_ID 0
152#define SEC_DRAM_ID 1
153
154#if BL32_RAM_LOCATION_ID == SEC_SRAM_ID
155# define BL32_MEM_BASE BL_RAM_BASE
156# define BL32_MEM_SIZE BL_RAM_SIZE
157# define BL32_BASE BL32_SRAM_BASE
158# define BL32_LIMIT BL32_SRAM_LIMIT
159#elif BL32_RAM_LOCATION_ID == SEC_DRAM_ID
160# define BL32_MEM_BASE SEC_DRAM_BASE
161# define BL32_MEM_SIZE SEC_DRAM_SIZE
162# define BL32_BASE BL32_DRAM_BASE
163# define BL32_LIMIT BL32_DRAM_LIMIT
164#else
165# error "Unsupported BL32_RAM_LOCATION_ID value"
166#endif
Jens Wiklander52c798e2015-12-07 14:37:10 +0100167
168#define NS_IMAGE_OFFSET 0x60000000
169
David Cunadoc1503122018-02-16 21:12:58 +0000170#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
171#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
Michalis Pappasba861122018-02-28 14:36:03 +0800172#define MAX_MMAP_REGIONS 10
Jens Wiklander52c798e2015-12-07 14:37:10 +0100173#define MAX_XLAT_TABLES 6
174#define MAX_IO_DEVICES 3
175#define MAX_IO_HANDLES 4
176
177/*
178 * PL011 related constants
179 */
180#define UART0_BASE 0x09000000
181#define UART1_BASE 0x09040000
182#define UART0_CLK_IN_HZ 1
183#define UART1_CLK_IN_HZ 1
184
185#define PLAT_QEMU_BOOT_UART_BASE UART0_BASE
186#define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ
187
188#define PLAT_QEMU_CRASH_UART_BASE UART1_BASE
189#define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ
190
191#define PLAT_QEMU_CONSOLE_BAUDRATE 115200
192
193#define QEMU_FLASH0_BASE 0x04000000
194#define QEMU_FLASH0_SIZE 0x04000000
195
196#define PLAT_QEMU_FIP_BASE QEMU_FLASH0_BASE
197#define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH0_SIZE
198
199#define DEVICE0_BASE 0x08000000
Hongbo Zhangbdcbf2a2018-04-19 14:42:23 +0800200#define DEVICE0_SIZE 0x01000000
Jens Wiklander52c798e2015-12-07 14:37:10 +0100201#define DEVICE1_BASE 0x09000000
Michalis Pappas8e235152018-03-03 18:26:11 +0800202#define DEVICE1_SIZE 0x00041000
Jens Wiklander52c798e2015-12-07 14:37:10 +0100203
204/*
205 * GIC related constants
206 */
207
208#define GICD_BASE 0x8000000
209#define GICC_BASE 0x8010000
Hongbo Zhangbdcbf2a2018-04-19 14:42:23 +0800210#define GICR_BASE 0x80A0000
Jens Wiklander52c798e2015-12-07 14:37:10 +0100211
212
213#define QEMU_IRQ_SEC_SGI_0 8
214#define QEMU_IRQ_SEC_SGI_1 9
215#define QEMU_IRQ_SEC_SGI_2 10
216#define QEMU_IRQ_SEC_SGI_3 11
217#define QEMU_IRQ_SEC_SGI_4 12
218#define QEMU_IRQ_SEC_SGI_5 13
219#define QEMU_IRQ_SEC_SGI_6 14
220#define QEMU_IRQ_SEC_SGI_7 15
221
Hongbo Zhang32338ec2018-04-19 13:06:07 +0800222/******************************************************************************
223 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
224 * interrupts.
225 *****************************************************************************/
226#define PLATFORM_G1S_PROPS(grp) \
227 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \
228 grp, GIC_INTR_CFG_EDGE), \
229 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
230 grp, GIC_INTR_CFG_EDGE), \
231 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
232 grp, GIC_INTR_CFG_EDGE), \
233 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
234 grp, GIC_INTR_CFG_EDGE), \
235 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
236 grp, GIC_INTR_CFG_EDGE), \
237 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
238 grp, GIC_INTR_CFG_EDGE), \
239 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
240 grp, GIC_INTR_CFG_EDGE), \
241 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
242 grp, GIC_INTR_CFG_EDGE)
243
244#define PLATFORM_G0_PROPS(grp)
245
Jens Wiklander52c798e2015-12-07 14:37:10 +0100246/*
247 * DT related constants
248 */
249#define PLAT_QEMU_DT_BASE NS_DRAM0_BASE
Jerome Forissier15ab24c2018-10-18 16:41:25 +0200250#define PLAT_QEMU_DT_MAX_SIZE 0x100000
Jens Wiklander52c798e2015-12-07 14:37:10 +0100251
252/*
253 * System counter
254 */
255#define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16)
256
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100257#endif /* PLATFORM_DEF_H */