XiaoDong Huang | 83f79a8 | 2019-06-13 10:55:50 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __SOC_H__ |
| 8 | #define __SOC_H__ |
| 9 | |
| 10 | #include <plat_private.h> |
| 11 | |
| 12 | #ifndef BITS_WMSK |
| 13 | #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) |
| 14 | #endif |
| 15 | |
| 16 | enum plls_id { |
| 17 | APLL_ID = 0, |
| 18 | DPLL_ID, |
| 19 | CPLL_ID, |
| 20 | NPLL_ID, |
| 21 | GPLL_ID, |
| 22 | END_PLL_ID, |
| 23 | }; |
| 24 | |
| 25 | enum pll_mode { |
| 26 | SLOW_MODE, |
| 27 | NORM_MODE, |
| 28 | DEEP_SLOW_MODE, |
| 29 | }; |
| 30 | |
| 31 | /*************************************************************************** |
| 32 | * SGRF |
| 33 | ***************************************************************************/ |
| 34 | #define SGRF_SOC_CON(i) ((i) * 0x4) |
| 35 | #define SGRF_DMAC_CON(i) (0x30 + (i) * 0x4) |
| 36 | |
| 37 | #define SGRF_MST_S_ALL_NS 0xffffffff |
| 38 | #define SGRF_SLV_S_ALL_NS 0xffff0000 |
| 39 | #define DMA_IRQ_BOOT_NS 0xffffffff |
| 40 | #define DMA_PERI_CH_NS_15_0 0xffffffff |
| 41 | #define DMA_PERI_CH_NS_19_16 0x000f000f |
| 42 | #define DMA_MANAGER_BOOT_NS 0x00010001 |
| 43 | #define DMA_SOFTRST_REQ BITS_WITH_WMASK(1, 0x1, 12) |
| 44 | #define DMA_SOFTRST_RLS BITS_WITH_WMASK(0, 0x1, 12) |
| 45 | |
| 46 | /*************************************************************************** |
| 47 | * GRF |
| 48 | ***************************************************************************/ |
| 49 | #define GRF_SOC_CON(i) (0x0400 + (i) * 4) |
| 50 | #define GRF_PD_VO_CON0 0x0434 |
| 51 | #define GRF_SOC_STATUS0 0x0480 |
| 52 | #define GRF_CPU_STATUS0 0x0520 |
| 53 | #define GRF_CPU_STATUS1 0x0524 |
| 54 | #define GRF_SOC_NOC_CON0 0x0530 |
| 55 | #define GRF_SOC_NOC_CON1 0x0534 |
| 56 | |
| 57 | #define CKECK_WFE_MSK 0x1 |
| 58 | #define CKECK_WFI_MSK 0x10 |
| 59 | #define CKECK_WFEI_MSK 0x11 |
| 60 | |
| 61 | #define GRF_SOC_CON2_NSWDT_RST_EN 12 |
| 62 | |
| 63 | /*************************************************************************** |
| 64 | * DDR FIREWALL |
| 65 | ***************************************************************************/ |
| 66 | #define FIREWALL_DDR_FW_DDR_RGN(i) ((i) * 0x4) |
| 67 | #define FIREWALL_DDR_FW_DDR_MST(i) (0x20 + (i) * 0x4) |
| 68 | #define FIREWALL_DDR_FW_DDR_CON_REG 0x40 |
| 69 | #define FIREWALL_DDR_FW_DDR_RGN_NUM 8 |
| 70 | #define FIREWALL_DDR_FW_DDR_MST_NUM 6 |
| 71 | |
| 72 | #define PLAT_MAX_DDR_CAPACITY_MB 4096 |
| 73 | #define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base)) |
| 74 | |
| 75 | /*************************************************************************** |
| 76 | * cru |
| 77 | ***************************************************************************/ |
| 78 | #define CRU_MODE 0xa0 |
| 79 | #define CRU_MISC 0xa4 |
| 80 | #define CRU_GLB_CNT_TH 0xb0 |
| 81 | #define CRU_GLB_RST_ST 0xb4 |
| 82 | #define CRU_GLB_SRST_FST 0xb8 |
| 83 | #define CRU_GLB_SRST_SND 0xbc |
| 84 | #define CRU_GLB_RST_CON 0xc0 |
| 85 | |
| 86 | #define CRU_CLKSEL_CON 0x100 |
| 87 | #define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + (i) * 4) |
| 88 | #define CRU_CLKSEL_CON_CNT 60 |
| 89 | |
| 90 | #define CRU_CLKGATE_CON 0x200 |
| 91 | #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + (i) * 4) |
| 92 | #define CRU_CLKGATES_CON_CNT 18 |
| 93 | |
| 94 | #define CRU_SOFTRST_CON 0x300 |
| 95 | #define CRU_SOFTRSTS_CON(n) (CRU_SOFTRST_CON + ((n) * 4)) |
| 96 | #define CRU_SOFTRSTS_CON_CNT 12 |
| 97 | |
| 98 | #define CRU_AUTOCS_CON0(id) (0x400 + (id) * 8) |
| 99 | #define CRU_AUTOCS_CON1(id) (0x404 + (id) * 8) |
| 100 | |
| 101 | #define CRU_CONS_GATEID(i) (16 * (i)) |
| 102 | #define GATE_ID(reg, bit) ((reg) * 16 + (bit)) |
| 103 | |
| 104 | #define CRU_GLB_SRST_FST_VALUE 0xfdb9 |
| 105 | #define CRU_GLB_SRST_SND_VALUE 0xeca8 |
| 106 | |
| 107 | #define CRU_GLB_RST_TSADC_EXT 6 |
| 108 | #define CRU_GLB_RST_WDT_EXT 7 |
| 109 | |
| 110 | #define CRU_GLB_CNT_RST_MSK 0xffff |
| 111 | #define CRU_GLB_CNT_RST_1MS 0x5DC0 |
| 112 | |
| 113 | #define CRU_GLB_RST_TSADC_FST BIT(0) |
| 114 | #define CRU_GLB_RST_WDT_FST BIT(1) |
| 115 | |
| 116 | /*************************************************************************** |
| 117 | * pll |
| 118 | ***************************************************************************/ |
| 119 | #define CRU_PLL_CONS(id, i) ((id) * 0x20 + (i) * 4) |
| 120 | #define PLL_CON(i) ((i) * 4) |
| 121 | #define PLL_CON_CNT 5 |
| 122 | #define PLL_LOCK_MSK BIT(10) |
| 123 | #define PLL_MODE_SHIFT(id) ((id) == CPLL_ID ? \ |
| 124 | 2 : \ |
| 125 | ((id) == DPLL_ID ? 4 : 2 * (id))) |
| 126 | #define PLL_MODE_MSK(id) (0x3 << PLL_MODE_SHIFT(id)) |
| 127 | |
| 128 | #define PLL_LOCKED_TIMEOUT 600000U |
| 129 | |
| 130 | /*************************************************************************** |
| 131 | * GPIO |
| 132 | ***************************************************************************/ |
| 133 | #define SWPORTA_DR 0x00 |
| 134 | #define SWPORTA_DDR 0x04 |
| 135 | #define GPIO_INTEN 0x30 |
| 136 | #define GPIO_INT_STATUS 0x40 |
| 137 | #define GPIO_NUMS 4 |
| 138 | |
| 139 | /************************************************** |
| 140 | * secure timer |
| 141 | **************************************************/ |
| 142 | |
| 143 | /* chanal0~5 */ |
| 144 | #define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) |
| 145 | |
| 146 | #define TIMER_LOAD_COUNT0 0x0 |
| 147 | #define TIMER_LOAD_COUNT1 0x4 |
| 148 | |
| 149 | #define TIMER_CUR_VALUE0 0x8 |
| 150 | #define TIMER_CUR_VALUE1 0xc |
| 151 | |
| 152 | #define TIMER_CONTROL_REG 0x10 |
| 153 | #define TIMER_INTSTATUS 0x18 |
| 154 | |
| 155 | #define TIMER_DIS 0x0 |
| 156 | #define TIMER_EN 0x1 |
| 157 | |
| 158 | #define TIMER_FMODE (0x0 << 1) |
| 159 | #define TIMER_RMODE (0x1 << 1) |
| 160 | |
| 161 | #define TIMER_LOAD_COUNT0_MSK (0xffffffff) |
| 162 | #define TIMER_LOAD_COUNT1_MSK (0xffffffff00000000) |
| 163 | |
| 164 | void clk_gate_con_save(uint32_t *clkgt_save); |
| 165 | void clk_gate_con_restore(uint32_t *clkgt_save); |
| 166 | void clk_gate_con_disable(void); |
| 167 | |
| 168 | void secure_timer_init(void); |
| 169 | void secure_timer_disable(void); |
| 170 | void px30_soc_reset_config(void); |
| 171 | |
| 172 | #endif /* __SOC_H__ */ |