blob: 1405ca6fba961a4a24720c881083e15badfc6349 [file] [log] [blame]
Saurabh Gorecha70389ca2020-04-22 21:31:24 +05301/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7#include <assert.h>
8
9#include <arch_helpers.h>
10#include <bl31/bl31.h>
11#include <common/debug.h>
Julius Werner0375d322019-02-20 17:33:23 -080012#include <drivers/delay_timer.h>
13#include <lib/mmio.h>
Saurabh Gorecha70389ca2020-04-22 21:31:24 +053014#include <lib/psci/psci.h>
15
16#include <platform.h>
17#include <platform_def.h>
18#include <qti_cpu.h>
19#include <qti_plat.h>
20#include <qtiseclib_cb_interface.h>
21#include <qtiseclib_defs_plat.h>
22#include <qtiseclib_interface.h>
23
24#define QTI_LOCAL_PSTATE_WIDTH 4
25#define QTI_LOCAL_PSTATE_MASK ((1 << QTI_LOCAL_PSTATE_WIDTH) - 1)
26
Maulik Shah8388dea2023-02-14 13:03:24 +053027#if PSCI_OS_INIT_MODE
28#define QTI_LAST_AT_PLVL_MASK (QTI_LOCAL_PSTATE_MASK << \
29 (QTI_LOCAL_PSTATE_WIDTH * \
30 (PLAT_MAX_PWR_LVL + 1)))
31#endif
32
Saurabh Gorecha70389ca2020-04-22 21:31:24 +053033/* Make composite power state parameter till level 0 */
34#define qti_make_pwrstate_lvl0(lvl0_state, type) \
35 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
36
37/* Make composite power state parameter till level 1 */
38#define qti_make_pwrstate_lvl1(lvl1_state, lvl0_state, type) \
39 (((lvl1_state) << QTI_LOCAL_PSTATE_WIDTH) | \
40 qti_make_pwrstate_lvl0(lvl0_state, type))
41
42/* Make composite power state parameter till level 2 */
43#define qti_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, type) \
44 (((lvl2_state) << (QTI_LOCAL_PSTATE_WIDTH * 2)) | \
45 qti_make_pwrstate_lvl1(lvl1_state, lvl0_state, type))
46
47/* Make composite power state parameter till level 3 */
48#define qti_make_pwrstate_lvl3(lvl3_state, lvl2_state, lvl1_state, lvl0_state, type) \
49 (((lvl3_state) << (QTI_LOCAL_PSTATE_WIDTH * 3)) | \
50 qti_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, type))
51
52/* QTI_CORE_PWRDN_EN_MASK happens to be same across all CPUs */
53#define QTI_CORE_PWRDN_EN_MASK 1
54
55/* cpu power control happens to be same across all CPUs */
Andre Przywara23b57bb2022-11-14 10:39:48 +000056DEFINE_RENAME_SYSREG_RW_FUNCS(cpu_pwrctrl_val, S3_0_C15_C2_7)
Saurabh Gorecha70389ca2020-04-22 21:31:24 +053057
58const unsigned int qti_pm_idle_states[] = {
59 qti_make_pwrstate_lvl0(QTI_LOCAL_STATE_OFF,
60 PSTATE_TYPE_POWERDOWN),
61 qti_make_pwrstate_lvl0(QTI_LOCAL_STATE_DEEPOFF,
62 PSTATE_TYPE_POWERDOWN),
63 qti_make_pwrstate_lvl1(QTI_LOCAL_STATE_DEEPOFF,
64 QTI_LOCAL_STATE_DEEPOFF,
65 PSTATE_TYPE_POWERDOWN),
66 qti_make_pwrstate_lvl2(QTI_LOCAL_STATE_OFF,
67 QTI_LOCAL_STATE_DEEPOFF,
68 QTI_LOCAL_STATE_DEEPOFF,
69 PSTATE_TYPE_POWERDOWN),
70 qti_make_pwrstate_lvl3(QTI_LOCAL_STATE_OFF,
71 QTI_LOCAL_STATE_DEEPOFF,
72 QTI_LOCAL_STATE_DEEPOFF,
73 QTI_LOCAL_STATE_DEEPOFF,
74 PSTATE_TYPE_POWERDOWN),
75 0,
76};
77
78/*******************************************************************************
79 * QTI standard platform handler called to check the validity of the power
80 * state parameter. The power state parameter has to be a composite power
81 * state.
82 ******************************************************************************/
83int qti_validate_power_state(unsigned int power_state,
84 psci_power_state_t *req_state)
85{
86 unsigned int state_id;
87 int i;
88
89 assert(req_state);
90
91 /*
92 * Currently we are using a linear search for finding the matching
93 * entry in the idle power state array. This can be made a binary
94 * search if the number of entries justify the additional complexity.
95 */
96 for (i = 0; !!qti_pm_idle_states[i]; i++) {
Maulik Shah8388dea2023-02-14 13:03:24 +053097#if PSCI_OS_INIT_MODE
98 if ((power_state & ~QTI_LAST_AT_PLVL_MASK) ==
99 qti_pm_idle_states[i])
100#else
Saurabh Gorecha70389ca2020-04-22 21:31:24 +0530101 if (power_state == qti_pm_idle_states[i])
Maulik Shah8388dea2023-02-14 13:03:24 +0530102#endif
Saurabh Gorecha70389ca2020-04-22 21:31:24 +0530103 break;
104 }
105
106 /* Return error if entry not found in the idle state array */
107 if (!qti_pm_idle_states[i])
108 return PSCI_E_INVALID_PARAMS;
109
110 i = 0;
111 state_id = psci_get_pstate_id(power_state);
112
113 /* Parse the State ID and populate the state info parameter */
Maulik Shah8388dea2023-02-14 13:03:24 +0530114 for (i = QTI_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) {
115 req_state->pwr_domain_state[i] = state_id &
Saurabh Gorecha70389ca2020-04-22 21:31:24 +0530116 QTI_LOCAL_PSTATE_MASK;
117 state_id >>= QTI_LOCAL_PSTATE_WIDTH;
118 }
Maulik Shah8388dea2023-02-14 13:03:24 +0530119#if PSCI_OS_INIT_MODE
120 req_state->last_at_pwrlvl = state_id & QTI_LOCAL_PSTATE_MASK;
121#endif
Saurabh Gorecha70389ca2020-04-22 21:31:24 +0530122
123 return PSCI_E_SUCCESS;
124}
125
126/*******************************************************************************
127 * PLATFORM FUNCTIONS
128 ******************************************************************************/
129
130static void qti_set_cpupwrctlr_val(void)
131{
132 unsigned long val;
133
134 val = read_cpu_pwrctrl_val();
135 val |= QTI_CORE_PWRDN_EN_MASK;
136 write_cpu_pwrctrl_val(val);
137
138 isb();
139}
140
141/**
142 * CPU power on function - ideally we want a wrapper since this function is
143 * target specific. But to unblock teams.
144 */
145static int qti_cpu_power_on(u_register_t mpidr)
146{
147 int core_pos = plat_core_pos_by_mpidr(mpidr);
148
149 /* If not valid mpidr, return error */
150 if (core_pos < 0 || core_pos >= QTISECLIB_PLAT_CORE_COUNT) {
151 return PSCI_E_INVALID_PARAMS;
152 }
153
154 return qtiseclib_psci_node_power_on(mpidr);
155}
156
157static bool is_cpu_off(const psci_power_state_t *target_state)
158{
159 if ((target_state->pwr_domain_state[QTI_PWR_LVL0] ==
160 QTI_LOCAL_STATE_OFF) ||
161 (target_state->pwr_domain_state[QTI_PWR_LVL0] ==
162 QTI_LOCAL_STATE_DEEPOFF)) {
163 return true;
164 } else {
165 return false;
166 }
167}
168
169static void qti_cpu_power_on_finish(const psci_power_state_t *target_state)
170{
171 const uint8_t *pwr_states =
172 (const uint8_t *)target_state->pwr_domain_state;
173 qtiseclib_psci_node_on_finish(pwr_states);
174
175 if (is_cpu_off(target_state)) {
176 plat_qti_gic_cpuif_enable();
177 }
178}
179
180static void qti_cpu_standby(plat_local_state_t cpu_state)
181{
182}
183
184static void qti_node_power_off(const psci_power_state_t *target_state)
185{
186 qtiseclib_psci_node_power_off((const uint8_t *)
187 target_state->pwr_domain_state);
188 if (is_cpu_off(target_state)) {
189 plat_qti_gic_cpuif_disable();
190 qti_set_cpupwrctlr_val();
191 }
192}
193
Maulik Shah8388dea2023-02-14 13:03:24 +0530194#if PSCI_OS_INIT_MODE
195static int qti_node_suspend(const psci_power_state_t *target_state)
196{
197 qtiseclib_psci_node_suspend((const uint8_t *)target_state->
198 pwr_domain_state);
199 if (is_cpu_off(target_state)) {
200 plat_qti_gic_cpuif_disable();
201 qti_set_cpupwrctlr_val();
202 }
203 return PSCI_E_SUCCESS;
204}
205#else
Saurabh Gorecha70389ca2020-04-22 21:31:24 +0530206static void qti_node_suspend(const psci_power_state_t *target_state)
207{
208 qtiseclib_psci_node_suspend((const uint8_t *)target_state->
209 pwr_domain_state);
210 if (is_cpu_off(target_state)) {
211 plat_qti_gic_cpuif_disable();
212 qti_set_cpupwrctlr_val();
213 }
214}
Maulik Shah8388dea2023-02-14 13:03:24 +0530215#endif
Saurabh Gorecha70389ca2020-04-22 21:31:24 +0530216
217static void qti_node_suspend_finish(const psci_power_state_t *target_state)
218{
219 const uint8_t *pwr_states =
220 (const uint8_t *)target_state->pwr_domain_state;
221 qtiseclib_psci_node_suspend_finish(pwr_states);
222 if (is_cpu_off(target_state)) {
223 plat_qti_gic_cpuif_enable();
224 }
225}
226
227__dead2 void qti_domain_power_down_wfi(const psci_power_state_t *target_state)
228{
229
230 /* For now just do WFI - add any target specific handling if needed */
231 psci_power_down_wfi();
232 /* We should never reach here */
233}
234
Julius Werner0375d322019-02-20 17:33:23 -0800235static __dead2 void assert_ps_hold(void)
236{
237 mmio_write_32(QTI_PS_HOLD_REG, 0);
238 mdelay(1000);
239
240 /* Should be dead before reaching this. */
241 panic();
242}
243
Saurabh Gorecha70389ca2020-04-22 21:31:24 +0530244__dead2 void qti_system_off(void)
245{
Julius Werner0375d322019-02-20 17:33:23 -0800246 qti_pmic_prepare_shutdown();
247 assert_ps_hold();
Saurabh Gorecha70389ca2020-04-22 21:31:24 +0530248}
249
250__dead2 void qti_system_reset(void)
251{
Julius Werner0375d322019-02-20 17:33:23 -0800252 qti_pmic_prepare_reset();
253 assert_ps_hold();
Saurabh Gorecha70389ca2020-04-22 21:31:24 +0530254}
255
256void qti_get_sys_suspend_power_state(psci_power_state_t *req_state)
257{
258 int i = 0;
259 unsigned int state_id, power_state;
260 int size = ARRAY_SIZE(qti_pm_idle_states);
261
262 /*
263 * Find deepest state.
264 * The arm_pm_idle_states[] array has last element by default 0,
265 * so the real deepest state is second last element of that array.
266 */
267 power_state = qti_pm_idle_states[size - 2];
268 state_id = psci_get_pstate_id(power_state);
269
270 /* Parse the State ID and populate the state info parameter */
271 while (state_id) {
272 req_state->pwr_domain_state[i++] =
273 state_id & QTI_LOCAL_PSTATE_MASK;
274 state_id >>= QTI_LOCAL_PSTATE_WIDTH;
275 }
276}
277
278/*
279 * Structure containing platform specific PSCI operations. Common
280 * PSCI layer will use this.
281 */
282const plat_psci_ops_t plat_qti_psci_pm_ops = {
283 .pwr_domain_on = qti_cpu_power_on,
284 .pwr_domain_on_finish = qti_cpu_power_on_finish,
285 .cpu_standby = qti_cpu_standby,
286 .pwr_domain_off = qti_node_power_off,
287 .pwr_domain_suspend = qti_node_suspend,
288 .pwr_domain_suspend_finish = qti_node_suspend_finish,
289 .pwr_domain_pwr_down_wfi = qti_domain_power_down_wfi,
290 .system_off = qti_system_off,
291 .system_reset = qti_system_reset,
292 .get_node_hw_state = NULL,
293 .translate_power_state_by_mpidr = NULL,
294 .get_sys_suspend_power_state = qti_get_sys_suspend_power_state,
295 .validate_power_state = qti_validate_power_state,
296};
297
298/**
299 * The QTI Standard platform definition of platform porting API
300 * `plat_setup_psci_ops`.
301 */
302int plat_setup_psci_ops(uintptr_t sec_entrypoint,
303 const plat_psci_ops_t **psci_ops)
304{
305 int err;
306
307 err = qtiseclib_psci_init((uintptr_t)bl31_warm_entrypoint);
308 if (err == PSCI_E_SUCCESS) {
309 *psci_ops = &plat_qti_psci_pm_ops;
310 }
311
312 return err;
313}