Pankaj Gupta | 82bd843 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2021 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef PLAT_DEFAULT_DEF_H |
| 9 | #define PLAT_DEFAULT_DEF_H |
| 10 | |
| 11 | /* |
| 12 | * Platform binary types for linking |
| 13 | */ |
| 14 | #ifdef __aarch64__ |
| 15 | #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" |
| 16 | #define PLATFORM_LINKER_ARCH aarch64 |
| 17 | #else |
| 18 | #define PLATFORM_LINKER_FORMAT "elf32-littlearm" |
| 19 | #define PLATFORM_LINKER_ARCH arm |
| 20 | #endif /* __aarch64__ */ |
| 21 | |
| 22 | #define LS_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL |
| 23 | |
| 24 | /* NXP Platforms have DRAM divided into banks. |
| 25 | * DRAM0 Bank: Maximum size of this bank is fixed to 2GB |
| 26 | * DRAM1 Bank: Greater than 2GB belongs to bank1 and size of bank1 varies from |
| 27 | * one platform to other platform. |
| 28 | * DRAMn Bank: |
| 29 | * |
| 30 | * Except a few, all the platforms have 2GB size as DRAM0 BANK. |
| 31 | * Hence common for all the platforms. |
| 32 | * For platforms where DRAM0 Size is < 2GB, it is defined in platform_def.h |
| 33 | */ |
| 34 | #ifndef PLAT_DEF_DRAM0_SIZE |
| 35 | #define PLAT_DEF_DRAM0_SIZE 0x80000000 /* 2G */ |
| 36 | #endif |
| 37 | |
| 38 | /* This is common for all platforms where: */ |
| 39 | #ifndef NXP_NS_DRAM_ADDR |
| 40 | #define NXP_NS_DRAM_ADDR NXP_DRAM0_ADDR |
| 41 | #endif |
| 42 | |
Jiafei Pan | 0a7cf57 | 2021-09-10 19:19:32 +0800 | [diff] [blame] | 43 | /* 1 MB is reserved for dma of sd */ |
| 44 | #ifndef NXP_SD_BLOCK_BUF_SIZE |
| 45 | #define NXP_SD_BLOCK_BUF_SIZE (1 * 1024 * 1024) |
| 46 | #endif |
| 47 | |
| 48 | /* 64MB is reserved for Secure memory */ |
Pankaj Gupta | 82bd843 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 49 | #ifndef NXP_SECURE_DRAM_SIZE |
| 50 | #define NXP_SECURE_DRAM_SIZE (64 * 1024 * 1024) |
| 51 | #endif |
| 52 | |
| 53 | /* 2M Secure EL1 Payload Shared Memory */ |
| 54 | #ifndef NXP_SP_SHRD_DRAM_SIZE |
| 55 | #define NXP_SP_SHRD_DRAM_SIZE (2 * 1024 * 1024) |
| 56 | #endif |
| 57 | |
| 58 | #ifndef NXP_NS_DRAM_SIZE |
| 59 | /* Non secure memory */ |
| 60 | #define NXP_NS_DRAM_SIZE (PLAT_DEF_DRAM0_SIZE - \ |
| 61 | (NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE)) |
| 62 | #endif |
| 63 | |
Jiafei Pan | 0a7cf57 | 2021-09-10 19:19:32 +0800 | [diff] [blame] | 64 | #ifndef NXP_SD_BLOCK_BUF_ADDR |
| 65 | #define NXP_SD_BLOCK_BUF_ADDR (NXP_NS_DRAM_ADDR) |
| 66 | #endif |
| 67 | |
Pankaj Gupta | 82bd843 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 68 | #ifndef NXP_SECURE_DRAM_ADDR |
| 69 | #ifdef TEST_BL31 |
| 70 | #define NXP_SECURE_DRAM_ADDR 0 |
| 71 | #else |
| 72 | #define NXP_SECURE_DRAM_ADDR (NXP_NS_DRAM_ADDR + PLAT_DEF_DRAM0_SIZE - \ |
Jiafei Pan | 0a7cf57 | 2021-09-10 19:19:32 +0800 | [diff] [blame] | 73 | (NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE)) |
Pankaj Gupta | 82bd843 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 74 | #endif |
| 75 | #endif |
| 76 | |
| 77 | #ifndef NXP_SP_SHRD_DRAM_ADDR |
Jiafei Pan | 0a7cf57 | 2021-09-10 19:19:32 +0800 | [diff] [blame] | 78 | #define NXP_SP_SHRD_DRAM_ADDR (NXP_NS_DRAM_ADDR + PLAT_DEF_DRAM0_SIZE - \ |
| 79 | NXP_SP_SHRD_DRAM_SIZE) |
Pankaj Gupta | 82bd843 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 80 | #endif |
| 81 | |
| 82 | #ifndef BL31_BASE |
| 83 | /* 2 MB reserved in secure memory for DDR */ |
| 84 | #define BL31_BASE NXP_SECURE_DRAM_ADDR |
| 85 | #endif |
| 86 | |
| 87 | #ifndef BL31_SIZE |
| 88 | #define BL31_SIZE (0x200000) |
| 89 | #endif |
| 90 | |
| 91 | #ifndef BL31_LIMIT |
| 92 | #define BL31_LIMIT (BL31_BASE + BL31_SIZE) |
| 93 | #endif |
| 94 | |
| 95 | /* Put BL32 in secure memory */ |
| 96 | #ifndef BL32_BASE |
| 97 | #define BL32_BASE (NXP_SECURE_DRAM_ADDR + BL31_SIZE) |
| 98 | #endif |
| 99 | |
| 100 | #ifndef BL32_LIMIT |
| 101 | #define BL32_LIMIT (NXP_SECURE_DRAM_ADDR + \ |
| 102 | NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE) |
| 103 | #endif |
| 104 | |
| 105 | /* BL33 memory region */ |
| 106 | /* Hardcoded based on current address in u-boot */ |
| 107 | #ifndef BL33_BASE |
| 108 | #define BL33_BASE 0x82000000 |
| 109 | #endif |
| 110 | |
| 111 | #ifndef BL33_LIMIT |
| 112 | #define BL33_LIMIT (NXP_NS_DRAM_ADDR + NXP_NS_DRAM_SIZE) |
| 113 | #endif |
| 114 | |
| 115 | /* |
| 116 | * FIP image defines - Offset at which FIP Image would be present |
| 117 | * Image would include Bl31 , Bl33 and Bl32 (optional) |
| 118 | */ |
| 119 | #ifdef POLICY_FUSE_PROVISION |
| 120 | #ifndef FUSE_BUF |
| 121 | #define FUSE_BUF ULL(0x81000000) |
| 122 | #endif |
| 123 | |
| 124 | #ifndef FUSE_SZ |
| 125 | #define FUSE_SZ 0x80000 |
| 126 | #endif |
| 127 | #endif |
| 128 | |
| 129 | #ifndef MAX_FIP_DEVICES |
| 130 | #define MAX_FIP_DEVICES 2 |
| 131 | #endif |
| 132 | |
| 133 | #ifndef PLAT_FIP_OFFSET |
| 134 | #define PLAT_FIP_OFFSET 0x100000 |
| 135 | #endif |
| 136 | |
| 137 | #ifndef PLAT_FIP_MAX_SIZE |
| 138 | #define PLAT_FIP_MAX_SIZE 0x400000 |
| 139 | #endif |
| 140 | |
| 141 | /* Check if this size can be determined from array size */ |
| 142 | #if defined(IMAGE_BL2) |
| 143 | #ifndef MAX_MMAP_REGIONS |
| 144 | #define MAX_MMAP_REGIONS 8 |
| 145 | #endif |
| 146 | #ifndef MAX_XLAT_TABLES |
| 147 | #define MAX_XLAT_TABLES 6 |
| 148 | #endif |
| 149 | #elif defined(IMAGE_BL31) |
| 150 | #ifndef MAX_MMAP_REGIONS |
| 151 | #define MAX_MMAP_REGIONS 9 |
| 152 | #endif |
| 153 | #ifndef MAX_XLAT_TABLES |
| 154 | #define MAX_XLAT_TABLES 9 |
| 155 | #endif |
| 156 | #elif defined(IMAGE_BL32) |
| 157 | #ifndef MAX_MMAP_REGIONS |
| 158 | #define MAX_MMAP_REGIONS 8 |
| 159 | #endif |
| 160 | #ifndef MAX_XLAT_TABLES |
| 161 | #define MAX_XLAT_TABLES 9 |
| 162 | #endif |
| 163 | #endif |
| 164 | |
| 165 | /* |
| 166 | * ID of the secure physical generic timer interrupt used by the BL32. |
| 167 | */ |
| 168 | #ifndef BL32_IRQ_SEC_PHY_TIMER |
| 169 | #define BL32_IRQ_SEC_PHY_TIMER 29 |
| 170 | #endif |
| 171 | |
| 172 | #endif /* PLAT_DEFAULT_DEF_H */ |